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| TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CA25FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP92CA25 CMOS 32-bit Microcontroller TMP92CA25FG/JTMP92CA25 1. Outline and Device Characteristics The TMP92CA25 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CA25 has a high-performance CPU (900/H1 CPU) and various built-in I/Os. The TMP92CA25FG is housed in a 144-pin flat package. The JTMP92CA25 is a chip form product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) * * * * Compatible with TLCS-900/L1 instruction code 16 Mbytes of linear address space General-purpose register and register banks Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz) RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070208EBP * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 92CA25-1 2007-02-28 TMP92CA25 (3) Internal memory * * * * Internal RAM: 10 Kbytes (can be used for program, data and display memory) Internal ROM: 0 Kbytes (used as boot program) Expandable up to 512 Mbytes (shared program/data area) Can simultaneously support 8,- 16- or 32-bit width external data bus ... dynamic data bus sizing Chip select output: 4 channels (4) External memory expansion (5) Memory controller * (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 1 channels * * * * * * * * * * UART/synchronous mode IrDA ver.1.0 (115 kbps) mode selectable I2C bus mode only I2S bus mode/SIO mode selectable (Master, transmission only) 32-byte FIFO buffer Supports monochrome for STN Built-in RAM LCD driver Supported only SPI mode for SD card Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM Supported not only operate as RAM and Data for LCD display but also programming directly from SDRAM Based on TC8521A (9) Serial bus interface: 1 channel: 1 channel (10) I2S (Inter-IC sound) interface: 1 channel (11) LCD controller (12) SPI controller (13) SDRAM controller: 1 channel (14) Timer for real-time clock (RTC) * (15) Key-on wakeup (Interrupt key input) (16) 10-bit AD converter (Built-in Sample Hold circuit): 4 channels (17) Touch screen interface * Available to reduce external components (18) Watchdog timer (19) Melody/alarm generator * * Melody: Output of clock 4 to 5461 Hz Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt 92CA25-2 2007-02-28 TMP92CA25 (20) MMU * * * * * Expandable up to 512 Mbytes (3 local area/8 bank method) Independent bank for each program, read data, write data and LCD display data 9 CPU interrupts: Software interrupt instruction and illegal instruction (21) Interrupts: 49 interrupt 34 internal interrupts: Seven selectable priority levels 7 external interrupts: Seven selectable priority levels (6-edge selectable) RD (21) Input/output ports: 84 pins (Except Data bus (16bit), Address bus (24bit) and (22) NAND flash interface: 2 channels * * * * * * * * * * * Direct NAND flash connection capability ECC (error detection) calculation (for SLC- type) Three HALT modes: IDLE2 (programmable), IDLE1, STOP Each pin status programmable for stand-by mode pin) (23) Stand-by function (24) Triple-clock controller Clock doubler (PLL) supplies 40 system-clock from external 10MHz oscillator to CPU Clock gear function: Select high-frequency clock fc to fc/16 RTC (fs = 32.768 kHz) VCC = 3.0 V to 3.6 V (fc max = 40 MHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz) 144-pin QFP (P-LQFP144 -1616-0.40C) 144-pin chip form is also available. For details, contact your local Toshiba sales representative. (25) Operating voltage: (26) Package: 92CA25-3 2007-02-28 TMP92CA25 PG0 to PG1 (AN0 to AN1) AN2/MX (PG2) AN3/MY/ ADTRG (PG3) AVCC, AVSS VREFH, VREFL (PX, INT4) P96 (PY, INT5) P97 (TXD0) PF0 (RXD0) PF1 (SCLK0) PF2 (I2SCKO, TXD0) P90 (I2SDO, RXD0) P91 (I2SWS, SCLK0) P92 (SDA) P93 (SCL) P94 (CLK32KO) P95 10-bit 4-channel AD converter Touch screen I/F (TSI) Serial I/O SIO0 900/H1 CPU XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC F PLL H-OSC Clock gear L-OSC RTCVCC DVCC [3] DVSS [3] X1 X2 BE XT1 XT2 RESET AM0 AM1 Interrupt controller D0 to D7 Port 1 P10 to P17 (D8 to D15) A0 to A7 A8 to A15 Port 6 P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P73 (EA24) P74 (EA25) P75 (R/ W , NDR/ B ) P76 ( WAIT ) IS 2 SBI (I Cbus) 2 Watchdog timer MMU 8-bit timer (TIMERA0) (TA1OUT, INT0) PC0 8-bit timer (TIMERA1) 8-bit timer (TIMERA2) (TA3OUT, INT1) PC1 8-bit timer (TIMERA3) 16-bit timer (TIMERB0) Port 7 (TB0OUT0, INT2) PC2 (INT3) PC3 (SPDI) PK4 (SPDO) PK5 ( SPCS ) PK6 (SPCLK) PK7 PC4 PC5 PF3 PF4 PF5 PF6 (LCP0) PK0 (LLP) PK1 (LFR) PK2 (LBCD) PK3 PL0 to PL5 (LD0 to LD5) (LD6, BUSRQ ) PL6 (LD7, BUSAK ) PL7 ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (NDALE) PJ5 (NDCLE) PJ6 (SDCKE) PJ7 (SDCLK) PF7 NAND flash I/F (2 channel) SPI controller P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA ) P83 ( CS3 ) P84 ( CSZB , ND0CE ) P85 ( CSZC , ND1CE ) P86 ( CSZD ) P87 ( CSZE ) PC7 ( CSZF , EA25) PA0 to PA7 (KI0 to KI7) PC6 (KO8,EA24) PN0 to PN7 (KO0 to KO7) PM2 ( ALARM , MLDALM ) Port C Port F Port 8 LCD controller Keyboard I/F 10-KB RAM Port N Port L RTC SDRAM controller Melody/ Alarm out PM1 (MLDALM) Figure 1.1 TMP92CA25 Block Diagram 92CA25-4 2007-02-28 TMP92CA25 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CA25FG, their names and functions are as follows: 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CA25FG. 140 135 130 125 120 115 VREFL VREFH PG0, AN0 PG1, AN1 PG2, AN2, MX PG3, AN3, ADTRG , MY P96, PX, INT4 P97, PY, INT5 PA3, KI3 PA4, KI4 PA5, KI5 PA6, KI6 PA7, KI7 P90, TXD0, I2SCKO P91, RXD0, I2SDO P92, SCLK0, CTS0 , I2SWS P93, SDA P94, SCL P95, CLK32KO PC2, TB0OUT0, INT2 PL0, LD0 PL1, LD1 PL2, LD2 PL3, LD3 PL4, LD4 PL5, LD5 PL6, LD6 PL7, LD7 PK0, LCP0 PK1, LLP PK2, LFR PK3, LBCD PM2, ALARM , MLDALM PM1, MLDALM XT1 XT2 1 110 AVCC AVSS PA2, KI2 PA1, KI1 PA0, KI0 PJ7, SDCKE PJ6, NDCLE PJ5, NDALE PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR PJ1, SDCAS, SRLUB PJ0, SDRAS, SRLLB PF7, SDCLK PC1, TA3OUT, INT1 PC0, TA1OUT, INT0 PF2, SCLK0, CTS0 PF1, RXD0 PF0, TXD0 PC7, CSZF, EA25 P87, CSZE P86, CSZD P85, CSZC, ND1CE P84, CSZB, ND0CE P83, CS3 P82, CS2, CSZA P81, CS1, SDCS PC6, KO8, EA24 P80, CS0 P76, WAIT P75, RW, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE P71, WRLL, NDRE P70, RD 105 5 100 10 15 TMP92CA25FG QFP144 95 90 20 Top View 85 25 80 30 75 35 40 45 50 55 60 65 70 P67, A23 P66, A22 P65, A21 P64, A20 DVCC3 P63, A19 P62, A18 P61, A17 P60, A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF6 PF5 DVSS3 PF4 PF3 PK7, SPCLK PK6, SPCS PK5, SPDO PK4, SPDI PN7, KO7 PN6, KO6 Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) PC3, INT3 DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10, D8 P11, D9 P12, D10 P13, D11 P14, D12 P15, D13 P16, D14 P17, D15 PN0, KO0 PN1, KO1 PN2, KO2 PN3, KO3 PN4, KO4 PN5, KO5 RTCVCC PC4 PC5 DVCC1 X1 DVSS1 X2 AM0 AM1 RESET BE 92CA25-5 2007-02-28 TMP92CA25 2.2 PAD Assignment (Chip size 4.98 mm x 5.61 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: m Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name VREFL VREFH PG0 PG1 PG2 PG3 P96 P97 PA3 PA4 PA5 PA6 PA7 P90 P91 P92 P93 P94 P95 PC2 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PK0 PK1 PK2 PK3 PM2 PM1 XT1 XT2 RTCVCC X point -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -2363 -1986 -1853 -1732 -1612 -1499 -1386 -1261 -972 -872 -772 -672 -572 Y point 2309 2189 1934 1593 1493 1393 1293 1192 1088 988 888 788 688 587 487 387 287 187 87 -13 -113 -213 -313 -413 -514 -614 -714 -814 -914 -1014 -1114 -1215 -1473 -1594 -1935 -2313 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14 P15 P16 P17 PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7 PK4 PK5 PK6 PK7 PF3 PF4 DVSS3 PF5 PF6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 X point -447 -297 -172 -72 28 128 228 328 429 529 629 729 829 929 1029 1129 1229 1329 1429 1529 1630 1753 1873 1994 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 Y point -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2678 -2313 -2049 -1708 -1587 -1472 -1359 -1243 -1131 -1012 -885 -749 -639 -530 -420 -311 -199 -88 23 134 245 356 473 589 705 Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name A13 A14 A15 P60 P61 P62 P63 DVCC3 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P80 PC6 P81 P82 P83 P84 P85 P86 P87 PC7 PF0 PF1 PF2 PC0 PC1 PF7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PA0 PA1 PA2 AVSS AVCC X point 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 2359 1994 1874 1753 1633 1527 1420 1316 1211 1104 999 893 787 682 574 468 363 259 154 50 -55 -158 -261 -364 -467 -568 -669 -771 -872 -972 -1074 -1175 -1278 -1379 -1499 -1860 -1985 Y point 822 939 1055 1171 1288 1400 1514 1643 1779 1902 2027 2309 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 BE PC4 PC5 DVCC1 X1 DVSS1 X2 AM0 AM1 RESET PC3 92CA25-6 2007-02-28 TMP92CA25 2.3 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Pin Name D0 to D7 P10 to P17 D8 to D15 A0 to A7 A8 to A15 P60 to P67 A16 to A23 P70 RD Number of Pins 8 8 8 8 8 1 I/O I/O I/O I/O Output Output I/O Output Output Output I/O Output Output I/O Data: Data bus 0 to 7 Function Port 1: I/O port input or output specifiable in units of bits Data: Data bus 8 to 15 Address: Address bus 0 to 7 Address: Address bus 8 to 15 Port 6: I/O port input or output specifiable in units of bits Address: Address bus 16 to 23 Port70: Output port Read: Outputs strobe signal to read external memory Port 71: I/O port Write: Output strobe signal for writing data on pins D0 to D7 NAND flash read: Outputs strobe signal to read external NAND flash Port 72: I/O port Write: Output strobe signal for writing data on pins D8 to D15 Write Enable for NAND flash Port 73: Output port Extended Address 24 Port 74: Output port Extended Address 25 Port 75: I/O port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle NAND flash ready (1)/Busy (0) input Port 76: I/O port Wait: Signal used to request CPU bus wait P71 WRLL NDRE 1 P72 WRLU NDWE 1 Output Output Output Output Output Output I/O Output Input I/O Input P73 EA24 P74 EA25 P75 R/ W 1 1 1 NDR/ B P76 WAIT 1 92CA25-7 2007-02-28 TMP92CA25 Table 2.3.2 Pin Names and Functions (2/5) Pin Name P80 CS0 Number of Pins 1 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Output Output I/O Input Output I/O I/O Input Output I/O I/O I/O I/O Output Output Input Input Output Input Input Output Input Input Function Port80: Output port Chip select 0: Outputs "low" when address is within specified address area Port81: Output port Chip select 1: Outputs "low" when address is within specified address area Chip select for SDRAM: Outputs "0" when address is within SDRAM address area Port82: Output port Chip select 2: Outputs "Low" when address is within specified address area Expand chip select: ZA: Outputs "0" when address is within specified address area Port83: Output port Chip select 3: Outputs "low" when address is within specified address area Port84: Output port Expand chip select: ZB: Outputs "0" when address is within specified address area Chip select for NAND flash 0: Outputs "0" when NAND flash 0 is enabled Port85: Output port Expand chip select: ZC: Outputs "0" when address is within specified address area Chip select for NAND flash 1: Outputs "0" when NAND flash 1 is enabled Port86: Output port Expand chip select: ZD: outputs "0" when address is within specified address area Port87: Output port Expand chip select: ZE: Outputs "0" when address is within specified address area Port90: I/O port Serial 0 send data: Open-drain output programmable 2 I S clock output Port91: I/O port (Schmitt-input) Serial 0 receive data 2 I S data output Port92: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) 2 I S word select output Port 93: I/O port I C data I/O Port 94: I/O port I C clock I/O Port95: Output port Output fs (32.768 kHz) clock Port 96: Input port (Schmitt-input) Interrupt request pin4: Interrupt request with programmable rising/falling edge X-Plus: Pin connectted to X+ for touch screen panel Port 97: Input port (Schmitt-input) Interrupt request pin5: Interrupt request with programmable rising/falling edge Y-Plus: Pin connectted to Y+ for touch screen panel Port: A0 to A7 port: Pin used to input ports (Schmitt input, with pull-up resistor) Key input 0 to 7: Pin used for key-on wakeup 0 to 7 2 2 P81 CS1 SDCS 1 P82 CS2 CSZA 1 P83 CS3 1 P84 CSZB ND0CE 1 P85 CSZC ND1CE 1 P86 CSZD 1 1 P87 CSZE P90 TXD0 I2SCKO P91 RXD0 I2SDO P92 SCLK0 CTS0 1 1 1 I2SWS P93 SDA P94 SCL P95 CLK32KO P96 INT4 PX P97 INT5 PY PA0 to PA7 KI0 to KI7 1 1 1 1 1 8 92CA25-8 2007-02-28 TMP92CA25 Table 2.3.3 Pin Names and Functions (3/5) Pin Name PC0 INT0 TA1OUT PC1 INT1 TA3OUT PC2 INT2 TB0OUT0 PC3 INT3 PC4 to PC5 PC6 KO8 EA24 PC7 CSZF Number of Pins 1 I/O I/O Input Output I/O Port C0: I/O port (Schmitt-input) Function Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge 8-bit timer 1 output: Timer 1 output Port C1: I/O port (Schmitt-input) Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge 8-bit timer 3 output: Timer 3 output Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Timer B0 output Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge Port C4 to C5: U/O port Port C6: I/O port Key Output 8: Pin used of key-scan strobe (Open-drain output programmable) Extended Address 24 Port C7: I/O port Expand chip select: ZF: Outputs "0" when address is within specified address area Extended Address 25 Port F0: I/O port (Schmitt-input) Serial 0 send data: Open-drain output programmable Port F1: I/O port (Schmitt-input) Serial 0 receive data Port F2: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) Port F7: Output port Clock for SDRAM (When SDRAM is not used, SDCLK can be used as system clock) Port G0 to G1 port: Pin used to input ports Analog input 0 to 1: Pin used to Input to AD conveter Port G2 port: Pin used to input ports Analog input 2: Pin used to Input to AD conveter X-Minus: Pin connectted to X- for touch screen panel Port G3 port: Pin used to input ports Analog input 3: Pin used to input to AD conveter Y-Minus: Pin connectted to Y- for touch screen panel AD trigger: Signal used to request AD start 1 Input Output I/O 1 Input Output I/O Input I/O I/O Output Output I/O 1 2 1 1 Output Output I/O Output I/O Input I/O I/O Input Output Output Input Input Input Input Output Input Input Output Intput EA25 PF0 TXD0 PF1 RXD0 PF2 SCLK0 CTS0 1 1 1 PF7 SDCLK PG0 to PG1 AN0 to AN1 PG2 AN2 MX PG3 AN3 MY ADTRG 1 2 1 1 92CA25-9 2007-02-28 TMP92CA25 Table 2.3.4 Pin Names and Functions (4/5) Pin Name PJ0 SDRAS SRLLB Number of Pins 1 I/O Output Output Output Output Port J0: Output port Row address strobe for SDRAM Data enable for SRAM on pins D0 to D7 Port J1: Output port Column address strobe for SDRAM Function PJ1 SDCAS SRLUB 1 Output Output Output Data enable for SRAM on pins D8 to D15 Port J2: Output port Write enable for SDRAM Write for SRAM: Strobe signal for writing data Port J3: Output port Data enable for SDRAM on pins D0 to D7 Port J4: Output port Data enable for SDRAM on pins D8 to D15 Port J5: I/O port Address latch enable for NAND flash Port J6: I/O port Command latch enable for NAND flash Port J7: Output port Clock enable for SDRAM Port K0: Output port LCD driver output pin Port K1: Output port LCD driver output pin Port K2: Output port LCD driver output pin Port K3: Output port LCD driver output pin Port K4: I/O port Data input pin for SD card Port K5: I/O port Data output pin for SD card PJ2 SDWE SRWR 1 Output Output Output Output Output Output I/O Output I/O Output Output Output Output Output Output Output Output Output Output Output I/O Input I/O Output PJ3 SDLLDQM PJ4 SDLUDQM PJ5 NDALE PJ6 NDCLE PJ7 SDCKE PK0 LCP0 PK1 LLP PK2 LFR PK3 LBCD PK4 SPDI PK5 SPDO PK6 1 1 1 1 1 1 1 1 1 1 1 SPCS PK7 SPCLK PL0 to PL3 LD0 to LD3 PL4 to PL5 LD4 to LD5 PL6 LD6 BUSRQ PL7 LD7 BUSAK 1 1 4 2 1 I/O Output I/O Output Output Output I/O Output I/O Output Input Port K6: I/O port Chip select pin for SD card Port K7: I/O port Clock output pin for SD card Port L0 to L3: Output port Data bus for LCD driver Port L4 to L5: I/O port Data bus for LCD driver Port L6: I/O port Data bus for LCD driver Bus request: request pin that set external memory bus to high-impedance (for External DMAC) Port L7: I/O port Data bus for LCD driver Bus acknowledge: this pin show that external memory bus pin is set to high-impedance by receiving BUSRQ (for External DMAC) 1 I/O Output Output 92CA25-10 2007-02-28 TMP92CA25 Table 2.3.5 Pin Names and Functions (5/5) Pin Name PM1 MLDALM PM2 ALARM Number of Pins 1 I/O Output Output Output Output Output I/O Output Port M1: Output port Melody/alarm output pin Port M2: Output port RTC alarm output pin Melody/alarm output pin (inverted) Port N0 to N7: I/O port Key out pin (Open-drain setting ) Operation mode: Function 1 8 MLDALM PN0 to PN7 KO0 to KO7 Fix to AM1 = "0", AM0 = "1" for 16-bit external bus starting AM0, AM1 2 Input Fix to AM1 = "1", AM0 = "0" for 32-bit external bus starting Fix to AM1 = "1", AM0 = "1" Prohibit setting Fix to AM1 = "0", AM0 = "0" Prohibit setting X1/X2 XT1/XT2 RESET 2 2 1 1 1 1 1 1 1 3 3 I/O I/O Input Input Input - High-frequency oscillator connection pins Low-frequency oscillator connection pins Reset: Initializes TMP92CA25 (with pull-up resistor, Schmitt input) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for RTC Back up enable pin: When power off DVCC and AVSS during RTC is operating, set to "L" level beforehand. Usually, this pin used to "H" level. (Schmitt input) Power supply pin for AD converter GND pin for AD converter (0 V) Power supply pins (All DVCC pins should be connected to the power supply pin) GND pins (0 V) (All DVSS pins should be connected to GND (0 V)) VREFH VREFL RTCVCC BE AVCC AVSS DVCC DVSS Input - - - - 92CA25-11 2007-02-28 TMP92CA25 3. 3.1 Operation This section describes the basic components, functions and operation of the TMP92CA25. CPU The TMP92CA25 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process instructions more quickly. The following is an outline of the CPU: Table 3.1.1 TMP92CA25 Outline Parameter Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Internal RAM TMP92CA25 24 bits 32 bits Max 20 MHz 1-clock access (50 ns at fSYS = 20MHz) 32-bit 1-clock access INTC, SDRAMC, 8-bit 2-clock access 16-bit 2-clock access 8-bit 56-clock access MEMC, NDFC, TSI, PORT I2S, SPIC, LCDC TMRA, TMRB, SIO, RTC, MLD/ALM, SBI, CGEAR, ADC Internal I/O External SRAM, Masked ROM 8- or 16-bit 2-clock access (waits can be inserted) 16-bit 1-clock access 8-bit 4-clock access (waits can be inserted) 1-clock (50 ns at fSYS = 20MHz) 2-clock (100 ns at fSYS = 20MHz) 12 bytes Compatible with TLCS-900/L1 (LDX instruction is deleted) Maximum mode only 8 channels External SDRAM External NAND flash Minimum instruction execution cycle Conditional jump Instruction queue buffer Instruction set CPU mode Micro DMA 92CA25-12 2007-02-28 TMP92CA25 3.1.2 Reset Operation When resetting the TMP92CA25, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 s at fc = 40 MHz). At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the system clock operates at 1.25 MHz (fc = 40 MHz). When the reset has been accepted, the CPU performs the following: * Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> PC<23:16> * * * data in location FFFF00H data in location FFFF01H data in location FFFF02H Sets the stack pointer (XSP) to 00000000H. Sets bits When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. * * Initializes the internal I/O registers as shown in the "Special Function Register" table in section 5. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal reset is released as soon as external reset is released. Memory controller operation cannot be ensured until the power supply becomes stable after power-on reset. External RAM data provided before turning on the TMP92CA25 may be corrupted because the control signals are unstable until the power supply becomes stable after power on reset. VCC (3.3 V) RESET High-frequency oscillation stabilized time +20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 92CA25-13 2007-02-28 fsys Sampling RESET fsysx(13.5~14.5) clock 0FFFF00H A23A0 CS0,1, 3 CS2 D0D31 DATA-IN DATA-IN Read RD SRxxB ((After reset released, starting 1 wait read cycle) Figure 3.1.2 TMP92CA25 Reset Timing Chart 92CA25-14 (Output mode) (Output mode) (Input mode) (Input mode) Pull up (Internal) High-Z D0D31 DATA-OUT WRxx Write SRWR SRxxB PF7 PJ3~PJ4, PJ7 PM1~PM2 P40~P47,P50~P57 P74~P72, PK0~PK3, PL0~PL3 PA0~PA7 TMP92CA25 2007-02-28 P71~P72, P75~P76, P90~P94, P96~P97, PC0~PC3, PC6~PC7, PF0~PF1, PG0~PG3, PJ5~PJ6, PL4~PL7, Note: This chart shows timing for a reset using a 32-bit external bus (AM1:0=10). TMP92CA25 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Operation Mode 16-bit external bus starting (MULTI 16 mode) 8-bit external bus starting (MULTI 8 mode) Prohibit setting Reserve (Toshiba test mode) Mode Setup Input Pin RESET AM1 0 1 1 0 AM0 1 0 1 0 92CA25-15 2007-02-28 TMP92CA25 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CA25. 000000H Internal I/O (8 Kbytes) 000100H 001D00H 002000H Internal RAM (10 Kbytes) Direct area (n) 64-Kbyte area (nn) 004800H 010000H External memory F00000H Provisional emulator control (64 Kbytes) F10000H (Note 1) 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) External memory FFFF00H Vector table (256 bytes) FFFFFFH ( = Internal area) (Note 2) Figure 3.2.1 Memory Map Note 1: The Provisional emulator control area, mapped F00000H to F0FFFFH after reset, is for emulator use and so is not available. When emulator WR signal and RD signal are asserted, this area is accessed. Ensure external memory is used. Note 2: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator. 92CA25-16 2007-02-28 TMP92CA25 3.3 Clock Function and Stand-by Function The TMP92CA25 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reduction circuits. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reduction circuits 3.3.6 Stand-by controller 92CA25-17 2007-02-28 TMP92CA25 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt Interrupt Instruction Interrupt STOP mode (Stops all circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) (fOSCH/gear value/2) STOP mode (Stops all circuits) Instruction SLOW mode (fs/2) Dual clock mode transition figure Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Instruction Note IDLE2 mode (I/O operate) Instruction Interrupt NORMAL mode (4 x fOSCH/gear value/2) Interrupt Instruction Interrupt Instruction SLOW mode (fs/2) Interrupt Instruction Interrupt IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) STOP mode (Stops all circuits) Instruction Instruction Note IDLE1 mode Instruction (Operate oscillator and PLL) Interrupt Using PLL (c) Triple clock mode transition figure Note 1: It is not possible to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL. (PLL start up/stop/change write to PLLCR0 Note 2: When shifting from NORMAL mode with use of PLL to NORMAL mode, execute the following setting in the same order. 1) Change CPU clock (PLLCR0 Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 92CA25-18 2007-02-28 TMP92CA25 3.3.1 Block Diagram of System Clock SYSCR0 /2 /4 T T0 fFPH /4 /8 fs /2 fc/2 fc/4 fc/8 fc/16 /8 /16 fSYS /2 fIO SYSCR1 SYSCR1 Clock-gear PLLCR0 fSYS fIO T0 TMRA0 to 3, TMRB0 Prescaler CPU RAM, ROM Interrupt controller SIO0 to SIO1 Prescaler LCDC Memory controller NAND flash controller IS I/O ports TSI SPIC 2 I2C bus Prescaler SDRAMC RTC fs MLD/ALM ADC WDT Figure 3.3.2 Block Diagram of System Clock 92CA25-19 2007-02-28 TMP92CA25 3.3.2 SFR 7 6 XTEN R/W 1 Highfrequency oscillator (fc) 0: Stop 1: Oscillation 5 4 3 2 WUEF R/W 0 Warm-up timer 0: Write don't care 1: Write 1 0 SYSCR0 (10E0H) Bit symbol Read/Write After reset Function XEN 1 Lowfrequency oscillator (fs) 0: Stop 1: Oscillation start timer 0: Read end warm-up 1: Read do not end warm-up 7 SYSCR1 (10E1H) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK 0 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Select Select gear value of high-frequency (fc) system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H) Bit symbol Read/Write After reset Function - R/W 0 Always write "0" 6 5 WUPTM1 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 1 1 0 01: 2 /input frequency 10: 2 /input frequency 11: 2 /input frequency 16 14 8 Note 1: The unassigned registers, SYSCR0 Figure 3.3.3 SFR for System Clock 92CA25-20 2007-02-28 TMP92CA25 7 EMCCR0 (10E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON EMCCR1 (10E4H) Bit symbol Read/Write After reset Function EMCCR2 (10E5H) Bit symbol Read/Write After reset Function 6 5 4 3 2 EXTIN 0 1: External clock 1 DRVOSCH R/W 1 fc oscillator driver ability 1: Normal 0: Weak 0 DRVOSCL 1 fs oscillator driver ability 1: Normal 0: Weak Switch the protect ON/OFF by writing the following to 1st-KEY, 2nd-KEY 1st-KEY: write in sequence EMCCR1 = 5AH, EMCCR2 = A5H 2nd-KEY: write in sequence EMCCR1 = A5H, EMCCR2 = 5AH Note: When restarting the oscillator from the stop oscillation state (e.g. restarting the oscillator in STOP mode), set EMCCR0 Figure 3.3.4 SFR for System Clock 92CA25-21 2007-02-28 TMP92CA25 7 PLLCR0 (10E8H) Bit symbol Read/Write After reset Function 6 FCSEL R/W 0 Select fc clock 0: fOSCH 1: fPLL 5 LUPFG R 0 Lock up timer status flag 0: Not end 1: End 4 3 2 1 0 Note: Ensure that the logic of PLLCR0 7 PLLCR1 (10E9H) Bit symbol Read/Write After reset Function PLLON R/W 0 Control on/off 0: OFF 1: ON 6 5 4 3 2 1 0 Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) Bit symbol Read/Write After reset Function 1 Px7D 6 Px6D 1 5 Px5D 1 4 Px4D R/W 1 3 Px3D 1 2 Px2D 1 1 Px1D 1 0 Px0D 1 Output/input buffer drive-register for stand-by mode (Purpose and use) This register is used to set each pin status at stand-by mode. All ports have registers of the format shown above. ("x" indicates the port name.) For each register, refer to "3.5 Function of ports". Before "Halt" instruction is executed, set each register according to the expected pin-status. They will be effective after the CPU has executed the "Halt" instruction. This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). The output/input buffer control table is shown below. OE 0 0 1 1 Note 1: PxnD 0 1 0 1 Output Buffer OFF OFF OFF ON Input Buffer OFF ON OFF OFF OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD denotes the bit number of PORTx. Figure 3.3.6 SFR for Drive Register 92CA25-22 2007-02-28 TMP92CA25 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 at fOSCH = 40 MHz, fs = 32.768 kHz Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to Normal Mode 6.4 (s) 409.6 (s) 1.638 (ms) Change to Slow Mode 7.8 (ms) 500 (ms) 2000 (ms) 92CA25-23 2007-02-28 TMP92CA25 Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR SET RES 10E0H 10E1H 10E2H (SYSCR2), 0 X 1 1 - - X X B ; 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) ; ; ; ; ; ; Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. 16 X: Don't care, -: No change Counts up by fSYS Counts up by fs 92CA25-24 2007-02-28 TMP92CA25 Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 10E0H 10E1H 10E2H (SYSCR2), 0 X 1 0 - - X X B ; 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) ; ; ; ; ; ; Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. 14 X: Don't care, -: No change 92CA25-25 2007-02-28 TMP92CA25 (2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 SYSCR1 EQU LD LD X: Don't care 10E1H (SYSCR1), XXXX0000B (DUMMY), 00H ; ; Changes fSYS to fc/2. Dummy instruction (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed 92CA25-26 2007-02-28 TMP92CA25 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed before use. As with an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by a 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency range for PLL The input frequency range (High-frequency oscillation) for PLL is as follows: fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD X: Don't care 10E8H 10E9H (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), 1XXXXXXXB ; ; ; X1XXXXXXB ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. Counts up by fOSCH During lock up After lock up 92CA25-27 2007-02-28 TMP92CA25 Example 2: PLL stopping PLLCR0 PLLCR1 EQU EQU LD LD X: Don't care 92CA25-28 2007-02-28 TMP92CA25 Limitations on the use of PLL 1. It is not possible to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). PLL should be controlled in the NORMAL mode. 2. When stopping PLL operation during PLL use, execute the following settings in the same order. LD LD (PLLCR0), 00H (PLLCR1), 00H ; ; Change the clock fPLL to fOSCH PLL stop 3. When stopping the high-frequency oscillator during PLL use, stop PLL before stopping the high-frequency oscillator. Examples of settings are shown below: (1) Start up/change control (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) (SYSCR0), 2, (SYSCR0) NZ, WUP (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), 11---1--B; ; ; ----0---B; 1-------B; ; ; -1------B; High-frequency oscillator start/warm-up start Check for warm-up end flag Change the system clock fs to fOSCH PLL start-up/lock up start Check for lock up end flag Change the system clock fOSCH to fPLL LD WUP: BIT JR LD LD LUP: BIT JR LD (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator Operate) High-frequency oscillator operation mode (fOSCH) PLL start up PLL use mode (fPLL) LD LD LUP: BIT JR LD (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), ----0---B; 1-------B; ; ; -1------B; Change the system clock fs to fOSCH PLL start-up/lock up start Check for lock up end flag Change the system clock fOSCH to fPLL (Error) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) High-frequency oscillator start up PLL start up PLL use mode (fPLL) LD WUP: BIT JR LD LUP: BIT JR LD LD (SYSCR0), 2, (SYSCR0) NZ, WUP (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), (SYSCR1), 11---1--B; ; ; 1-------B; ; ; -1------B; ----0---B; High-frequency oscillator start/warm-up start Check for warm-up end flag PLL start-up/lock up start Check for lock up end flag Change the internal clock fOSCH to fPLL Change the system clock fs to fPLL 92CA25-29 2007-02-28 TMP92CA25 (2) Change/stop control (OK) PLL use mode (fPLL) High-frequency oscillator operation mode (fOSCH) PLL Stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop (PLLCR0), (PLLCR1), (SYSCR1), (SYSCR0), -0------B; 0-------B; ----1---B; 0-------B; Change the system clock fPLL to fOSCH PLL stop Change the system clock fOSCH to fs High-frequency oscillator stop LD LD LD LD (Error) PLL use mode (fPLL) Low-frequency oscillator operation mode (fs) PLL stop High-frequency oscillator stop LD LD LD LD (SYSCR1), (PLLCR0), (PLLCR1), (SYSCR0), - - - - 1 - - - B ; Change the system clock fPLL to fs - 0 - - - - - - B ; Change the internal clock (fC) fPLL to fOSCH 0 - - - - - - - B ; PLL stop 0 - - - - - - - B ; High-frequency oscillator stop (OK) PLL use mode (fPLL) Set the STOP mode High-frequency oscillator operation mode (fOSCH) PLL stop Halt (High-frequency oscillator stop) LD LD LD HALT (SYSCR2), (PLLCR0), (PLLCR1), ----01--B; -0------B; 0-------B; ; Set the STOP mode (This command can be executed before use of PLL) Change the system clock fPLL to fOSCH PLL stop Shift to STOP mode (Error) PLL use mode (fPLL) Set the STOP mode Halt (High-frequency oscillator stop) LD HALT (SYSCR2), ----01--B; ; Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode 92CA25-30 2007-02-28 TMP92CA25 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents When above function is used, set EMCCR0 and EMCCR2 registers (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator X1 pin Enable oscillation EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing "0" to EMCCR0 92CA25-31 2007-02-28 TMP92CA25 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 Resonator EMCCR0 (Setting method) The drive ability of the oscillator is reduced by writing 0 to the EMCCR0 fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 92CA25-32 2007-02-28 TMP92CA25 (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (memory controller, MMU) which prevent fetch operations. Runaway error handling is also facilitated by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, MEMCR0 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2 Protection state can be confirmed by reading EMCCR0 92CA25-33 2007-02-28 TMP92CA25 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 PxDR (xxxxH) Bit symbol Read/Write After reset Function (Purpose and use) * * * * * * This register is used to set each pin status at stand-by mode. All ports have this registers of the format shown above. ("x" indicates the port name.) For each register, refer to 3.5 function of ports. Before "Halt" instruction is executed, set each register according to the expected pin status. They will be effective after the CPU has executed the "Halt" instruction. This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). The Output/Input buffer control table is shown below. 1 1 1 1 Px7D 6 Px6D 5 Px5D 4 Px4D R/W 3 Px3D 1 2 Px2D 1 1 Px1D 1 0 Px0D 1 Output/input buffer drive register for stand-by mode OE 0 0 1 1 Note 1: PxnD 0 1 0 1 Output Buffer OFF OFF OFF ON Input Buffer OFF ON OFF OFF OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: "n" in PxnD denotes the bit number of PORTx The subsequent actions performed in each mode are as follows: 1. IDLE2: only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.2 shows the register setting operation during IDLE2 mode. Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRB0 SIO0 I C bus AD converter WDT 2 SFR TA01RUN 2. 3. IDLE1: Only the oscillator, RTC (real-time clock) and MLD continue to operate. STOP: All internal circuits stop operating. 92CA25-34 2007-02-28 TMP92CA25 The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO, SBI Block AD converter WDT I2S, LCDC, SDRAMC, Interrupt controller, USBC, RTC, MLD Operate Operate Available to select operation block Stop IDLE2 11 Stop IDLE1 10 Depend on PxDR register setting STOP 01 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination of the states of the interrupt mask register 92CA25-35 2007-02-28 TMP92CA25 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode INTWD Source of Halt State Clearance INT0 to INT4 (Note 1) INTALM0 to INTALM4 INTTA0 to INTTA3, Interrupt INTTB0 to INTTB1 INTRX0 to INTTX0, INTSBI INTTBO0, INTI2S INTAD, INT5, INTSPI INTKEY INTRTC INTLCD RESET Interrupt Enabled (Interrupt level) (Interrupt mask) IDLE2 Interrupt Disabled (Interrupt level) < (Interrupt mask) IDLE2 - IDLE1 x x x x x x STOP x *1 x x x x x *1 *1 x IDLE1 - STOP - x x x x x x x x *1 x x x x x x x *1 *1 x Initialize LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT instruction. x: Cannot be used to release the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This combination is not available. *1: Release of the HALT mode is executed after warm-up time has elapsed. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH LD LD LD EI LD HALT (PCFC), 01H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; ; ; ; ; ; Sets PC0 to INT0. Selects INT0 interrupt rising edge. Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 INT0 interrupt routine RETI 820FH LD XX, XX 92CA25-36 2007-02-28 TMP92CA25 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release IDLE2 mode Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release IDLE1 mode Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CA25-37 2007-02-28 TMP92CA25 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release STOP mode Figure 3.3.9 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Example of Warm-up Time after Releasing STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR1 0 (fc) 1 (fs) SYSCR2 6.4 s 7.8 ms 8 10 (214) 409.6 s 500 ms 11 (216) 1.638 ms 2000 ms 92CA25-38 2007-02-28 TMP92CA25 Table 3.3.6 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/2/STOP) Input Function Port Name Name When the CPU is operating During Reset When used as Function pin ON upon external read - - ON - When used as Input pin - OFF - - ON - When used When used When When used as as used as as Function pin Input pin Function pin Input pin - OFF - - OFF - - D0~D7 P10~P17 P60~P67 P71~P72 P75 P76 P90 P91 P92 P93~P94 P96 * P97 PA0~PA7* 1 1 D0~D7 D8~D15 - - NDR / B WAIT OFF - RXD0 CTS0 , SCLK0 SDA, SCL INT4 INT5 KI0-KI7 INT0 INT1 INT2 INT3 - - RXD0 CTS0 ON ON ON ON ON OFF PC0 PC1 PC2 PC3 PC4~PC7 PF0 PF1 PF2 PG0~PG2* 2 OFF - - - ON - ON - ON - ON ON - ON ON upon port read ON - ON - ON - ON - ON - ON OFF - ON - OFF - OFF - ON - SCLK0 - ADTRG PG3 *2 OFF OFF PJ5~PJ6 PK4 PK5~PK5 PL4~PL5, PL7 PL6 PN0~PN7 BE RESET - SPDI - - BUSRQ AM0, AM1 X1, XT1 - - - - - input pin is not driven. ON - IDLE2/IDLE1:ON, STOP:OFF *2: AIN input does not cause a current to flow through the buffer. ON: The buffer is always turned on. A current flows the input buffer if the *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. -: No applicable 92CA25-39 2007-02-28 TMP92CA25 Table 3.3.7 Output Buffer State Table (1/2) Output Buffer State When the CPU is operating Port Name Output Function Name During Reset When used as Function pin ON upon external write When used as Output pin - ON - ON OFF ON OFF ON OFF In HALT mode (IDLE1/2/STOP) D0~D7 P10~P17 A0~A15 P60~P67 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 D0~D7 OFF D8~D15 A16~A15, A16~A23 RD WRLL , NDRE WRLU , NDWE EA24 EA25 R/W - CS0 - - - CS1 , SDCS CS2 , CSZA ON ON ON OFF CS3 CSZB , ND0CE CSZC , ND1CE CSZD CSZE ON ON OFF TXD0, I2SCKO I2SDO I2SWS SDA SCL CLK32KO PX PY OFF ON OFF - - - ON: The buffer is always turned on. OFF: The buffer is always turned off. -: Not applicable *1: Port having a pull-up/pull-down resistor. 92CA25-40 2007-02-28 TMP92CA25 Table 3.3.8 Output Buffer State Table (2/2) Output Buffer State When the CPU is operating Port Name Output Function Name During Reset When used as Output pin In HALT mode (IDLE1/2/STOP) When used as Function pin PC0 PC1 PC2 PC3 PC6 PC7 PF0 PF1 PF2 PF7 PG2 PG3 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0~PL3 PL4~PL6 PL7 PM1 PM2 PN0~PN7 X2 TA1OUT TA3OUT TB0OUT0 ON - OFF ON - ON OFF - ON ON - ON - - KO8, EA24 CSZF , EA25 TXD0 - SCLK0 SDCLK MX MY SDRAS SRLLB - - SDCAS , SRLUB SDWE , SRWR ON ON OFF ON OFF SDLLDQM SDLUDQM NDALE NDCLE SDCKE LCP LLP LFR LBCD ON ON - OFF - ON - OFF - SPDO SPCS SPCLK LD0~LD3 LD4~LD6 LD7, BUSAK MLDALM ON OFF ON MLDALM , ALARM KO0~KO7 OFF IDLE2/1:ON, ON - - STOP: output "H" IDLE2/1:ON, STOP: output "HZ" *1: Port having a pull-up/pull-down resistor. - - XT2 ON: The buffer is always turned on. OFF: The buffer is always turned off. -: Not applicable 92CA25-41 2007-02-28 TMP92CA25 3.4 Interrupts Interrupts are controlled by the CPU Interrupt mask register 92CA25-42 2007-02-28 TMP92CA25 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue "V" read interrupt request F/F clear Data transfer by micro DMA Micro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR COUNT = 0 NO YES Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CA25-43 2007-02-28 TMP92CA25 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register 92CA25-44 2007-02-28 TMP92CA25 Table 3.4.1 TMP92CA25 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Maskable Nonmaskable Type Interrupt Source and Source of Micro DMA Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction (Reserved) INTWD: Watchdog Timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input (TSI) INTALM0: ALM0 (8192 Hz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTP0: Protect0 (Write to special SFR) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 0 INTKEY: Key-on wakeup INTRTC: RTC (Alarm interrupt) INTTBO0: 16-bit timer 0 (Overflow) INTLCD: LCDC/LP pin INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) (Reserved) (Reserved) (Reserved) (Reserved) INT5: INT5 pin input INTI2S: I S (Channel 0) INTNDF0 (NAND flash controller channel 0) INTNDF1 (NAND flash controller channel 1) INTSPI: SPIC INTSBI: SBI (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 2 Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Micro Address Refer DMA Start to Vector Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H - (Note1) 0AH (Note 2) 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note 2) 21H 22H (Note 2) 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 92CA25-45 2007-02-28 TMP92CA25 Interrupt Source and Source of Micro DMA Request (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) Maskable INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) (Reserved) Default Priority 51 52 53 54 55 56 57 58 59 60 - to - Type Vector Value 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH Micro Address Refer DMA Start to Vector Vector FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH - to - Note 1: Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupts. Note 2: When initiating micro DMA, set at edge detect mode. 92CA25-46 2007-02-28 TMP92CA25 3.4.2 Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CA25 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented through the CPU, when the CPU is placed in a stand-by state by a Halt instruction, the requirements of the micro DMA will be ignored (pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. Note: When using the micro DMA transfer end interrupt, always write "1" to bit 7 of SIMC register. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e., interrupt requests should be disabled). If micro DMA and general purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 92CA25-47 2007-02-28 TMP92CA25 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts - the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state (1) fSYS A23 to A0 (2) (3) (4) (5) src dst Note: In fact, src and dst address are not output to A23 to A0 pins because they are internal RAM address. Figure 3.4.2 Timing for Micro DMA Cycle State (1), (2): Instruction fetch cycle (Prefetches the next instruction code) State (3): State (4): State (5): Micro DMA read cycle Micro DMA write cycle (The same as in state (1), (2)) 92CA25-48 2007-02-28 TMP92CA25 (2) Soft start function The TMP92CA25 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. (If write "0" to each bit, micro DMA doesn't operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write "1" to plural bits.) When writing again 1 to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by the DMAB register, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol Name DMA Request Address 109H (Prohibit RMW) 7 DREQ7 0 6 DREQ6 0 5 DREQ5 0 4 DREQ4 0 R/W 3 DREQ3 0 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr, r can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0 DMA destination address register 0 DMA counter register 0 DMA mode register 0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits DMA source address register 7 DMA destination address register 7 DMA counter register 7 DMA mode register 7 92CA25-49 2007-02-28 TMP92CA25 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAMn[4:0] 000zz Mode Description Destination INC mode (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Destination DEC mode (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source INC mode (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source DEC mode (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTCn Source and destination INC mode (DMADn+) (DMASn+) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination DEC mode (DMADn-) (DMASn-) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source and destination Fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTCn Execution State Number 5 states 001zz 5 states 010zz 5 states 011zz 5 states 100zz 6 states 101zz 6 states 110zz 5 states 11100 5 states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (Reserved) Note1: N stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (register value is decremented after transfer) "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. Note3: The execution state number shows number of best case (1-state memory access). 92CA25-50 2007-02-28 TMP92CA25 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bit of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in 92CA25-51 2007-02-28 Interrupt controller Interrupt request F/F S R V = 20H V = 24H CPU 1 Q Interrupt mask F/F RESET Interrupt request RESET interrupt vector read Decoder Priority encoder signal to CPU IFF2 to 0 3 3 INTRQ2 to 0 3 Interrupt level detect 1 7 6 6 A B C INTWD Priority setting register D Q CLR Interrupt request F/F Dn + 3 Interrupt request F/F 45 Interrupt vector generator Dn Dn + 1 EI 1 to 7 DI Interrupt request signal Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 If INTRQ2 to 0 IFF 2 to 0 then 1. INT0 Reset SQ R D0 D1 Interrupt vector read Micro DMA acknowledge D2 D3 D4 D5 D6 D7 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 INT1 INT2 INT3 INT4 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt vector read V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH 92CA25-52 8 input OR Soft start 8 51 S Selector Halt release Micro DMA counter 0 interrupt RESET INT01 to INT4, INTKEY,INTRTC, INTALM Micro DMA request INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 DQ CLR 6 INTTC0 DMA0V DMA1V : DMA7V if IFF = 7 then 0 3 3 RESET 0 1 2 3 4 5 6 7 A B C Micro DMA channel priority decoder Micro DMA channel specification TMP92CA25 2007-02-28 TMP92CA25 (1) Interrupt level setting registers Symbol Name INT0 & INTAD enable INT1 INTE12 & INT2 enable INT3 INTE34 & INT4 enable INT5 INTE5I2S & INTI2S enable INTTA0 INTETA01 & INTTA1 enable INTTA2 INTETA23 & INTTA3 enable INTTB0 INTETB01 & INTTB1 enable INTTBO0 INTETBO0 Address 7 IADC R 0 I2C R 0 I4C R 0 II2SC R 0 ITA1C R 0 ITA3C R 0 ITB1C R 0 - 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 INTI2S II2SM2 0 ITA1M2 0 ITA3M2 0 ITB1M2 0 - - 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 II2SM1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITB1M1 R/W 0 - 4 IADM0 0 I2M0 0 I4M0 0 II2SM0 0 ITA1M0 0 ITA3M0 0 ITB1M0 0 - 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 ITA0C R 0 ITA2C R 0 ITB0C R 0 ITBO0C 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITB0M2 0 INTTBO0 ITBO0M2 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITB0M1 R/W 0 ITBO0M1 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITB0M0 0 ITBO0M0 INTE0AD F0H D0H D1H EBH INTTA1 (TMRA1) D4H INTTA0 (TMRA0) INTTA3 (TMRA3) D5H INTTA2 (TMRA2) INTTB1 (TMRB1) D8H INTTB0 (TMRB0) (Overflow) enable DAH R Note: Always write 0 0 ITX0M0 0 ITX1M0 0 IA1M0 0 IA3M0 0 IA0C R 0 IA2C R 0 0 0 IRX0C R 0 - 0 - - 0 INTTX0 R/W 0 INTRX0 IRX0M2 IRX0M1 R/W 0 - 0 - IRX0M0 0 INTRX0 INTES0 & INTTX0 enable DBH ITX0C R 0 ITX1C R 0 INTALM0 & INTALM1 enable IA1C R 0 INTALM2 & INTALM3 enable IA3C R 0 0 0 0 0 ITX0M2 ITX0M1 R/W 0 INTTX1 INTESPI INTSPI enable E0H ITX1M2 ITX1M1 R/W 0 INTALM1 INTEALM01 Note: Always write 0 INTALM0 IA0M2 IA0M1 R/W 0 INTALM2 IA2M2 IA2M1 R/W 0 0 IA2M0 0 IA0M0 E5H IA1M2 IA1M1 R/W 0 INTALM3 INTEALM23 E6H IA3M2 IA3M1 R/W 0 92CA25-53 2007-02-28 TMP92CA25 Symbol Name INTALM4 enable Address 7 - 6 - - 5 - 4 - 3 IA4C R 0 2 INTALM4 IA4M2 0 INTRTC IRM2 0 INTKEY IKM2 0 INTLCD ILCDM2 0 INTNDF0 IN0M2 0 INTP0 IP0M2 0 1 IA4M1 R/W 0 IRM1 R/W 0 IKM1 R/W 0 ILCDM1 R/W 0 IN0M1 R/W 0 IP0M1 R/W 0 0 IA4M0 0 IRM0 0 IKM0 0 ILCDM0 0 IN0M0 0 IP0M0 0 INTEALM4 E7H Note: Always write 0 - INTERTC INTRTC enable E8H - - - - IRC R 0 Note: Always write 0 - INTEKEY INTKEY enable E9H - - - - IKC R 0 Note: Always write 0 - INTELCD INTLCD enable EAH - - - - ILCD1C R 0 Note: Always write 0 INTNDF0 & INTNDF1 enable INTNDF1 ECH IN1C R 0 - 0 - INTEP0 INTP0 enable EEH - - - IN1M2 IN1M1 R/W 0 0 IN1M0 INTEND01 IN0C R 0 IP0C R 0 Note: Always write 0 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92CA25-54 2007-02-28 TMP92CA25 Symbol Name INTTC0 & INTTC1 enable INTTC2 & INTTC3 enable INTTC4 & INTTC5 enable INTTC6 & INTTC7 enable Address 7 ITC1C R 0 ITC3C R 0 ITC5C R 0 ITC7C R 0 6 ITC1M2 0 ITC3M2 0 ITC5M2 0 ITC7M2 0 - - 5 ITC1M1 R/W 0 ITC3M1 R/W 0 ITC5M1 R/W 0 ITC7M1 R/W 0 - 4 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 - 3 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 ITCWD R 0 2 ITC0M2 0 ITC2M2 0 ITC4M2 0 ITC6M2 0 INTWD - - 1 ITC0M1 R/W 0 ITC2M1 R/W 0 ITC4M1 R/W 0 ITC6M1 R/W 0 - - 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 ITC6M0 0 - - INTTC1 (DMA1) F1H INTTC0 (DMA0) INTETC01 INTTC3 (DMA3) F2H INTTC2 (DMA2) INTETC23 INTTC5 (DMA5) F3H INTTC4 (DMA4) INTETC45 INTTC7 (DMA7) INTETC67 F4H INTTC6 (DMA6) INTWDT INTWD enable F7H - Note: Always write 0 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92CA25-55 2007-02-28 TMP92CA25 (2) External interrupt control Symbol Name Address 7 I5EDGE 0 F6H 6 I4EDGE 0 5 I3EDGE W 0 4 I2EDGE 0 3 I1EDGE 0 2 I0EDGE 0 1 I0LE R/W 0 0 - 0 Always write "0" IIMC Interrupt input mode control INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 (Prohibit edge 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising RMW) mode 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: INT0 level mode *INT0 level enable 0 Edge detect INT 1 "H" level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD LD NOP NOP NOP EI (IIMC), XXXXXX00B ; Switches from level to edge. (INTCLR), 0AH ; Clears interrupt request flag. ; Wait EI execution X: Don't care, -: No change. Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt Pin Name Mode Rising edge INT0 PC0 Falling edge High level Rising edge INT1 PC1 Falling edge Rising edge INT2 PC2 Falling edge Rising edge INT3 PC3 Falling edge Rising edge INT4 P96 Falling edge Rising edge INT5 P97 Falling edge Setting Method 92CA25-56 2007-02-28 TMP92CA25 (3) SIO receive interrupt control Symbol Name Address 7 - W SIO SIMC interrupt mode control F5H (Prohibit RMW) 0 Always write "0" (Note) 1 Always write "0" 6 5 4 3 2 1 - W 0 IR0LE 1 0: INTRX0 edge mode 1: INTRX0 level mode Note: When using the micro DMA transfer end interrupt, always write "1". INTRX0 rising edge enable 0 Edge detect INTRX0 1 "H" level INTRX0 92CA25-57 2007-02-28 TMP92CA25 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Symbol Name Interrupt clear control Clears interrupt request flag INT0. 6 CLRV6 0 Address F8H (Prohibit RMW) 7 CLRV7 5 CLRV5 0 4 CLRV4 W 0 3 CLRV3 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 0 Interrupt vector (5) Micro DMA start vector registers These registers assign micro DMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel's micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) 92CA25-58 2007-02-28 TMP92CA25 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 DMA4V4 0 DMA5V4 0 DMA6V4 0 DMA7V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 DMA4V3 0 DMA5V3 0 DMA6V3 0 DMA7V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 DMA4V2 0 DMA5V2 0 DMA6V2 0 DMA7V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA4V1 0 DMA5V1 0 DMA6V1 0 DMA7V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA4V0 0 DMA5V0 0 DMA6V0 0 DMA7V0 0 DMA0V start vector 100H 0 DMA1V5 101H 0 DMA2V5 102H 0 DMA3V5 103H 0 DMA4V5 104H 0 DMA5V5 105H 0 DMA6V5 106H 0 DMA7V5 107H 0 DMA0 start vector DMA1 DMA1V start vector R/W DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector DMA4 DMA4V start vector R/W DMA4 start vector DMA5 DMA5V start vector R/W DMA5 start vector DMA6 DMA6V start vector R/W DMA6 start vector DMA7 DMA7V start vector R/W DMA7 start vector 92CA25-59 2007-02-28 TMP92CA25 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name DMA burst Address 7 DBST7 6 DBST6 0 5 DBST5 0 4 DBST4 R/W 0 3 DBST3 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 DMAB 108H 0 1: DMA burst request 92CA25-60 2007-02-28 TMP92CA25 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be placed after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., "NOP" x 3 times). If it placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enabled before request flag is cleared. In the case of changing the value of the interrupt mask register INT0 level mode In level mode INT0 is not an edge triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H NOP NOP NOP EI ; Switches from level to edge. ; Wait EI execution LD (INTCLR), 0AH ; Clears interrupt request flag. INTRX In level mode (the register SIMC Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. ("H" "L") INTRX: Instructions which read the receive buffer. INTRX: Instructions which read the receive buffer. 92CA25-61 2007-02-28 TMP92CA25 3.5 Function of Ports The TMP92CA25 I/O port pins are shown in Table 3.5.1 and Table 3.5.2. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.5.3 to Table 3.5.5 list the I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) (R: PD = with programmable pull-down resistor, U = with pull-up resistor) Port Name Port 1 Port 6 Port 7 Pin Name P10 to P17 P60 to P67 P70 P71 P72 P73 P74 P75 P76 Number of Pins 8 8 1 1 1 1 1 1 1 I/O I/O I/O Output I/O I/O I/O I/O I/O I/O R - - - - - - - - - - - - - - - I/O Setting Bit Bit (Fixed) Bit Bit Bit Bit Bit Pin Name for Built-in Function D8 to D15 A16 to A23 RD WRLL , NDRE WRLU , NDWE EA24 EA25 R/ W , NDR/ B WAIT CS0 CS1 , SDCS CS2 , CSZA CS3 CSZB , WRUL , ND0CE CSZC , WRUU , ND1CE CSZD CSZE Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Port 8 P80 P81 P82 P83 P84 P85 P86 P87 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O Output Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output - - - - - - - - Port 9 P90 P91 P92 P93 P94 P95 P96 P97 TXD0, I2SCKO RXD0, I2SDO SCLK0, CTS0 , I2SWS SDA SCL CLK32KO INT4, PX INT5, PY KI0 to KI7 INT0, TA1OUT INT1, TA3OUT INT2, TB0OUT0 INT3 PD - Port A Port C PA0 to PA7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 U - - - - - - - - - - - - - - - - KO8, EA24 CSZF , EA25 Port F PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 TXD0 RXD0 SCLK0, CTS0 SDCLK 92CA25-62 2007-02-28 TMP92CA25 Table 3.5.2 Port Functions (2/2) (R: PD = with programmable pull-down resistor, U = with pull-up resistor) Port Name Port G Pin Name PG0 to PG1 PG2 PG3 Number of Pins 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 2 1 1 1 1 8 I/O Input Input Input Output Output Output Output Output I/O I/O Output Output Output Output Output I/O I/O I/O I/O Output I/O I/O I/O Output Output I/O R - - - - - - - - - - - - - - - - - - - - - - - - - - I/O Setting (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit (Fixed) Bit Bit Bit (Fixed) (Fixed) Bit Pin Name for Built-in Function AN0 to AN1 AN2, MX AN3, ADTRG , MY SDRAS , SRLLB SDCAS , SRLUB SDWE , SRWR Port J PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 SDLLDQM SDLUDQM NDALE NDCLE SDCKE LCP0 LLP LFR LBCD SPDI SPDO SPCS Port K PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 SPCLK LD0 to LD3 LD4 to LD5 LD6, BUSRQ LD7, BUSAK MLDALM ALARM , MLDALM Port L PL0 to PL3 PL4 to PL5 PL6 PL7 Port M Port N PM1 PM2 PN0 to PN7 KO0 to KO7 92CA25-63 2007-02-28 TMP92CA25 Table 3.5.3 I/O Registers and Specifications (1/3) X: Don't care Port Port 1 Pin Name P10 to P17 Input port Output port Specification I/O Register Pn X X X X X X X X X X 1 0 1 0 X X X X X X X X X X X X X X X X X X None 0 1 X 1 0 None 1 1 1 1 1 1 1 0 0 PnCR 0 1 X PnFC PnFC2 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 X 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 None None None D8 to D15 bus A0 to A7 output Port 6 P60 to P67 Input port Output port A16 to A23 output Port 7 P70 to P76 P71 to P76 P70 P71 Output port Input port RD output WRLL output NDRE output P72 WRLU output NDWE output P73 P74 P75 P76 Port 8 P80 to P87 P80 P81 P82 P83 P84 P85 P86 P87 EA24 output EA25 output R/ W output NDR/ B input WAIT input Output Port CS0 output CS1 output SDCS output CS2 output CSZA Output CS3 output CSZB output ND0CE output CSZC output ND1CE output CSZD output CSZE output 92CA25-64 2007-02-28 TMP92CA25 Table 3.5.4 I/O Registers and Specifications (2/3) X: Don't care Port Port 9 Pin Name P90 to P94, P96 to P97 P90 to P94 P95 P90 Input port Output port Specification Pn X X X X X X X X X X X X X X X X X X None X X X X X X X X X X 0 X 0 X X X X X X X X I/O Register PnCR 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 None None None 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 0 None PnFC PnFC2 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 None 0 0 1 None None None None None None None 0 1 0 1 None None 1 0 TXD0 output I2SCKO output TXD0 output (Open drain) P91 RXD0 input I2SDO output P92 SCLK0 output I2SWS output SCLK0, CTS0 input (Note1) P93 SDA I/O SDA I/O (Open drain) P94 SCL I/O SCL I/O (Open drain) P95 P96 P97 Port A Port C PA0 to PA7 PC0 to PC3 PC6 to PC7 PC0 PC1 PC2 CLK32KO output INT4 input INT5 input Input port KI0 to KI7 input Input port Output port INT0 input TA1OUT output INT1 input TA3OUT output INT2 input TB0OUT0 output PC3 PC6 PC7 Port F PF0 to PF6 PF0 toPF7 PF0 PF1 PF2 PF7 INT3 input KO8 output (Open drain) EA24 output CSZF output EA25 output Input port Output port TXD0 output TXD0 output (Open drain) RXD0 input SCLK0 output SCLK0, CTS0 input SDCLK output Note: To use P92-pin as SCLK0 input or CTS0 input, set "1" to PF 92CA25-65 2007-02-28 TMP92CA25 Table 3.5.5 I/O Registers and Specifications (3/3) X: Don't care Port Port G Pin Name PG0 to PG3 PG3 PG2 PG3 Input port Specification I/O Register Pn PnCR PnFC PnFC2 AN0 to AN3 input ADTRG input X None None None MX output MY output Output port Input port SDRAS , SRLLB output SDCAS , SRLUB output SDWE , SRWR output Port J PJ0 to PJ7 PJ5 to PJ6 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 X X X X X X 1 0 0 X X X X X X X X X X X X X X X X X X X 0 1 X X X 1 0 0 0 1 1 None 1 1 1 SDLLDQM output SDLUDQM output NDALE output NDCLE output SDCKE output Input port Output port Output port LCP0 output LLP output LFR output LBCD output SPDI input SPDO output SPCS output None 1 1 None 0 None 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 None None None Port K PK4 to PK7 PK0 to PK3 PK4 to PK7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 None 0 1 1 1 0 1 1 1 1 SPCLK output Input Port Output Port LD0 to LD7 output BUSRQ input Port L PL4 to PL7 PL0 to PL7 PL0 to PL7 PL6 PL7 BUSAK output Port M PM1 to PM2 PM1 PM2 Output Port MLDALM output MLDALM output ALARM output None 1 1 1 0 0 1 None Port N PN0 to PN7 Input Port Output Port (CMOS output) KO output (Open drain output) 0 1 1 None 92CA25-66 2007-02-28 TMP92CA25 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don't use this setting Data bus (D8 to D15) Data bus (D8 to D15) Input port P1CR register P1FC register External write enable P1 register S 0 D8 to D15 S Port read data 1 0 Selector 1 Selector P10 to P17 (D8 to D15) D8 to D15 External read enable Figure 3.5.1 Port 1 92CA25-67 2007-02-28 TMP92CA25 Port 1 register 7 P1 (0004H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to "0") Port 1 Control register 7 P1CR (0006H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 0: Input 1: Output Port 1 Function register 7 P1FC (0007H) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P1F W 0/1 Note 2 0: Port 1: Data bus (D8 to D15) Port 1 Drive register 7 P1DR (0081H) Bit symbol Read/Write After reset Function 1 1 1 1 P17D 6 P16D 5 P15D 4 P14D W 3 P13D 1 2 P12D 1 1 P11D 1 0 P10D 1 Input/Output buffer drive register for standby mode Note1: Read-modify-write is prohibited for P1CR and P1FC. Note2: It is set to "Port" or "Data bus" by AM pin setting. Figure 3.5.2 Register for Port 1 92CA25-68 2007-02-28 TMP92CA25 3.5.2 A0 to A7 A0 to A7 pin function is Address bus function only. Driver register is following register. Port 4 Drive register 7 P4DR (0084H) Bit symbol Read/Write After reset Function 1 1 1 1 P57D 6 P56D 5 P55D 4 P54D W 3 P53D 1 2 P52D 1 1 P51D 1 0 P50D 1 Input/Output buffer drive register for standby mode Figure 3.5.3 Driver register for A0 to A7 3.5.3 A8 to A15 A8 to A15 pin function is Address bus function only. Driver register is following register. Port 5 Drive register 7 P5DR (0085H) Bit symbol Read/Write After reset Function 1 1 1 1 P57D 6 P56D 5 P55D 4 P54D W 3 P53D 1 2 P52D 1 1 P51D 1 0 P50D 1 Input/Output buffer drive register for standby mode Figure 3.5.4 Drive register for A8 to A15 92CA25-69 2007-02-28 TMP92CA25 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). AM1 0 0 1 1 AM0 0 1 0 1 P6CR register Function Setting after Reset is Released Don't use this setting Address bus (A16 to A23) Address bus (A16 to A23) Input port P6FC register (Reserved) P6 register S 0 A16 to A23 S Port read data 1 0 Selector 1 Selector P60 to P67 (A16 to A23) Figure 3.5.5 Port 6 92CA25-70 2007-02-28 TMP92CA25 Port 6 register 7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Data from external port (Output latch register is cleared to "0") Port 6 Control register 7 P6CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 2 P62C 0 1 P61C 0 0 P60C 0 0: Input 1: Output Port 6 Function register 7 P6FC (001BH) Bit symbol Read/Write After reset Note 2 Function 0/1 0/1 0/1 0/1 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 2 P62F 1 P61F 0 P60F 0/1 0/1 0/1 0/1 0: Port 1: Address bus (A16 to A23) Port 6 Drive register 7 P6DR (0086H) Bit symbol Read/Write After reset Function 1 1 1 1 P67D 6 P66D 5 P65D 4 P64D W 3 P63D 1 2 P62D 1 1 P61D 1 0 P60D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write is prohibited for P6CR and P6FC. Note 2: It is set to "Port" or "Address bus" by AM pin setting. Figure 3.5.6 Register for Port 6 92CA25-71 2007-02-28 TMP92CA25 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function as interface pins for external memory. A reset initializes P70 pin to output port mode, and P71to P76 pin to input port mode. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don't use this setting RD pin RD pin P70 output port P7FC register P7 register 0 RD S P70( RD ) 1 Selector Port read data P7CR register P7FC register S 0 S NDRE , NDWE WRLL , WRLU P7 register 0 1 S 1 0 Selector 1 Selector P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) Port read data Figure 3.5.7 Port 7 92CA25-72 2007-02-28 TMP92CA25 P7CR register P7FC register S 0 1 Selector S Port read data 1 0 Selector P73 (EA24) P74 (EA25) P7 register EA24, EA25 P7CR register P7FC register S 0 1 Selector S Port read data 1 0 NDR/ B P75 (R/ W , NDR/ B ) P7 register R/ W P7CR register P7FC register P7 register P76 ( WAIT ) Port read data WAIT Figure 3.5.8 Port 7 92CA25-73 2007-02-28 TMP92CA25 Port 7 register 7 P7 (001CH) Bit symbol Read/Write After reset Data from external port (Output latch register is set to "1") 6 P76 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to "0") Data from external port (Output latch register is set to "1") 1 Port 7 Control register 7 P7CR (001EH) Bit symbol Read/Write After reset Function 0 0 0 6 P76C 5 P75C 4 P74C W 3 P73C 0 2 P72C 0 1 P71C 0 0 0: Input 1: Output Port 7 Function register 7 P7FC (001FH) Bit symbol Read/Write After reset Function 0 0: Input port 1: WAIT 0 0 6 P76F 5 P75F 4 P74F 3 P73F W 0 Refer to following table 2 P72F 0 1 P71F 0 0 P70F 0/1 Note 2 0: port 1: RD Port 7 Drive register 7 P7DR (0087H) Bit symbol Read/Write After reset Function P73 Setting NDWE output (at 6 P76D 1 5 P75D 1 4 P94D 1 3 P73D R/W 1 2 P72D 1 1 P71D 1 0 P70D 1 Input/Output buffer drive register for standby mode P71 Setting NDRE output at ( 1 P75 Setting (Reserved) 1 P74 Setting (Reserved) 0 Input port NDR/ B input (at 1 Output port R/ W output 0 Input port 1 Output port 1 WAIT input (Reserved) 1 (Reserved) EA25 output Note 1: Read-modify-write is prohibited for P7CR and P7FC. Note 2: It is set to "Port" or " RD " by AM pin setting. Note 3: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch. Order (1) (2) (3) Register P7 P7FC P7CR Bit2 0 1 1 Bit1 0 1 1 Figure 3.5.9 Register for Port 7 92CA25-74 2007-02-28 TMP92CA25 3.5.6 Port 8 (P80 to P87) Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to "0" and the output latches of P80 to P81, P83 to P87 to "1". Port 8 can also be set to function as an interface pin for external memory using function register P8FC. Writing "1" in the corresponding bit of P8FC and P8FC2 enables the respective functions. Resetting Reset Function control 2 P8FC2 write Internal data bus Function contol P8FC write Ouptut latch Selector P8 write P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA ) P83 ( CS3 ) P84 ( CSZB , ND0CE ) P85 ( CSZC , ND1CE ) P86 ( CSZD ) P87 ( CSZE ) P8 read "1", "1", "1", "1", ND0CE , ND1CE , "1", "1", "1", SDCS , CSZA , "1" CS0 , CS1 , CS2 , CS3 , CSZB , CSZC , CSZD , CSZE Figure 3.5.10 Port 8 92CA25-75 2007-02-28 TMP92CA25 Port 8 Register 7 P8 (0020H) Bit symbol Read/Write After reset 1 1 1 1 P87 6 P86 5 P85 4 P84 R/W 3 P83 1 2 P82 0 1 P81 1 0 P80 1 Port 8 Function Register 7 P8FC (0023H) Bit symbol Read/Write After reset Function 0 0: Port 1: CSZE 0 0: Port 1: CSZD 0 Refer to following table 0 Refer to following table P87F 6 P86F 5 P85F 4 P84F W 3 P83F 0 0: Port 1: CS3 2 P82F 0 Refer to following table 1 P81F 0 0: Port 1: CS1 0 P80F 0 0: Port 1: CS0 Port 8 Function Register 2 7 P8FC2 (0021H) Bit symbol Read/Write After reset Function 0 0 0 0 Refer to following table 0: 6 P86F2 5 P85F2 4 P84F2 W 3 P83F2 0 Always write "0" 2 P82F2 0 1 P81F2 0 0 P80F2 0 Always write "0" Refer to 0: Port 8 Drive Register 7 P8DR (0088H) Bit symbol Read/Write After reset Function 1 1 1 1 P87D 6 P86D 5 P85D 4 P84D R/W 3 P83D 1 2 P82D 1 1 P81D 1 0 P80D 1 Input/Output buffer drive register for standby mode P85 Setting CSZC output ND1CE output P84 Setting CSZB output ND0CE output P82 Setting CSZA output CS2 output 0 1 Reserved Note 1: Read-modify-write is prohibited for P8FC and P8FC2. Note 2: Don't write "1" to P8 CE for program memory by reset. Figure 3.5.11 Register for Port 8 92CA25-76 2007-02-28 TMP92CA25 3.5.7 Port 9 (P90 to P97) P90 to P94 are 5-bit general-purpose I/O ports. I/O can be set on a bit basis using the control register. Resetting sets P90 to P94 to input port and all bits of output latch to"1". P95 is 1-bit general-purpose output port and P96 to P97 are 2-bit general-purpose input ports. Setting the corresponding bits of P9FC enables the respective functions. Resetting resets the P9FC to "0", and sets all bits except P95 to input ports. (1) Port 90 (TXD0, I2SCKO), Port91 (RXD0, I2SDO), Port 92 (SCLK0, CTS0 I2SWS) Ports 90 to 92 are general-purpose I/O ports. They also function as either SIO0 or I2S. Each pin is detailed below. SIO mode (SIO0 module) P90 P91 P92 TXD0 (Data output) RXD0 (Data input) SCLK0 (Clock input or output) UART, IrDA mode (SIO0 module) TXD0 (Data output) RXD0 (Data input) CTS0 I2S mode (I S module) I2SCKO (Clock output) I2SDO (Data output) I2SWS (Word select output) 2 SIO mode (I2S module) I2SCKO (Clock output) I2SDO (Data output) (No use) (Clear to send) Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch Internal data bus S A Selector B S B Selector A P90 (TXD0, I2SCKO) SPDI input P9 write TXD0, I2SCKO output P9 read Figure 3.5.12 P90 92CA25-77 2007-02-28 TMP92CA25 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch Internal data bus S A Selector B S B Selector A (to Port F1) P91RXD0 input (to Port F2) P92SCLK0 input P91 (RXD0, I2SDO) P92 (SCLK0, CTS0 , I2SWS) P9 write I2SDO output SCLK0,I2SWS output P9 read Figure 3.5.13 P91 and P92 (2) P93 (SDA), P94 (SCL) Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch Internal data bus S A Selector B S B Selector A Open drain enable P9FC2 P93(SDA), P94(SCL) P9 write SDA, SCL output P9 read SDA, SCL input Figure 3.5.14 Port 93 and 94 92CA25-78 2007-02-28 TMP92CA25 (3) P95 (CLK32KO) Reset Direction control (on bit basis) P9CR write Internal data bus Funtcion control (on bit basis) P9FC write S Output latch S A Selector B P95 (CLK32KO) P9 write fs P9 read Figure 3.5.15 Port 95 (4) P96 (INT4, PX), P97 (INT5, PY) Internal data bus Reset Function control TSICR0 AVCC Switch for TSI Typ.20 P9 read P96 (INT4, PX) P97 (INT5, PY) TSICR1 Only for P96 INT4 INT5 TSICR0 Pull-down resistor typ.200k Figure 3.5.16 Port 96, 97 92CA25-79 2007-02-28 TMP92CA25 Port 9 Register 7 P9 (0024H) Bit symbol Read/Write After reset P97 R Data from external port 0 6 P96 5 P95 4 P94 3 P93 R/W 2 P92 1 P91 0 P90 Data from external port (Output latch register is set to "1") Port 9 Control Register 7 P9CR (0026H) Bit symbol Read/Write After reset Function 0 0 0 6 5 P95C 4 P94C 3 P93C W 2 P92C 0 1 P91C 0 0 P90C 0 Refer to following table Port 9 Function Register 7 P9FC (0027H) Bit symbol Read/Write After reset Function 0 0: Input port 1: INT5 6 P96F 0 0: Input port 1: INT4 5 P95F 0 4 P94F W 0 3 P93F 0 2 P92F 0 1 P91F 0 0 P90F 0 P97F Refer to following table P92 Setting CLK32KO output P91 Setting SCLK0, CTS0 input P90 Setting I2SDO output 1 0 Input port I2SCKO output 1 Output port TXD0 output Output port SCLK0 output 0 1 P94 Setting I2SWS output 1 0 Input port (Reserved) 1 0 Input port (Reserved) 1 Output port SDA I/O (Reserved) Port 9 Function Register 2 7 P9FC2 (0025H) Bit symbol Read/Write After reset Function 0 0: CMOS 1: Open drain 6 5 4 P94F2 W 3 P93F2 0 0: CMOS 1: Open drain 2 1 0 P90F2 W 0 0: CMOS 1: Open drain Port 9 Drive Register 7 P9DR (0089H) Bit symbol Read/Write After reset Function 1 1 1 1 P97D 6 P96D 5 P95D 4 P94D R/W 3 P93D 1 2 P92D 1 1 P91D 1 0 P90D 1 Output/Input buffer drive register for standby mode Note 1: Read modify write is prohibited for P9CR, P9FC and P9FC2. Note 2: When setting P97 and P96 pin to INT5 and INT4 input, set P9DR Figure 3.5.17 Register for Port 9 92CA25-80 2007-02-28 TMP92CA25 3.5.8 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit input general-purpose ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also, as a keyboard interface, operate a key-on wakeup function. The various functions can each be enabled by writing a "1" to the corresponding bit of the port A function register (PAFC). Resetting resets all bits of the register PAFC to "0" and sets all pins to be input port. INTKEY Edge detection PA0 to PA7 8-input OR Reset Key-on Enable (on bit basis) PAFC write Pull-up resistor Internal data bus PA read PA0 (KI0) PA1 (KI1) PA2 (KI2) PA3 (KI3) PA4 (KI4) PA5 (KI5) PA6 (KI6) PA7 (KI7) Figure 3.5.18 Port A When PAFC = "1", if the input of any of KI0 to KI7 pins fall down, an INTKEY interrupt is generated. An INTKEY interrupt can be used to release all HALT modes. 92CA25-81 2007-02-28 TMP92CA25 Port A Register 7 PA (0028H) Bit symbol Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port Port A Function Register 7 PAFC (002BH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Key input disable PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 0 2 PA2F 0 1 PA1F 0 0 PA0F 0 1: Key input enable Port A Drive register 7 PADR (008AH) Bit symbol Read/Write After reset Function 1 1 1 1 PA7D 6 PA6D 5 PA5D 4 PA4D W 3 PA3D 1 2 PA2D 1 1 PA1D 1 0 PA0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for PACR and PAFC. Figure 3.5.19 Register for Port A 92CA25-82 2007-02-28 TMP92CA25 3.5.9 Port C (PC0 to PC3, PC6 to PC7) PC0 to PC7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port C to an input port. In addition to functioning as a general-purpose I/O port, port C can also function as an output pin for timers (TA1OUT, TA3OUT and TB0OUT0), input pin for external interruption (INT0 to INT3), output pin for memory ( CSZF ), output pin for key (KO8). These settings are made using the function register PCFC. The edge select for external interruption is determined by the IIMC register in the interruption controller. (1) PC0 (INT0, TA1OUT) Reset Direction control Direction control (on bit basis) PCCR write Internal data bus Function control Function control (on bit basis) PCFC write S Output latch S A Selector B PC0 (INT0, TA1OUT) PC write TA1OUT S B Selector A Level/edge select and Rising/falling select IIMC PC read INT0 Figure 3.5.20 Port C0 92CA25-83 2007-02-28 TMP92CA25 (2) PC1 (INT1, TA3OUT), PC2 (INT2, TB0OUT0), PC3 (INT3, TB0OUT1) Reset Direction control (on bit basis) PCCR write Function control (on bit basis) PCFC write S Output latch S A Selector B Internal data bus PC1 (INT1, TA3OUT) PC2 (INT2, TB0OUT0) PC3 (INT3) PC write TA3OUT TB0OUT0 S B Selector A PC read INT1 to INT3 Rising/falling edge detection IIMC Figure 3.5.21 Port C1, C2, C3 (3) PC4, PC5 Reset Direction control (on bit basis) PCCR write Function control (on bit basis) Internal data bus PCFC write S Output latch PC4 PC5 PC write S B Selector A PC read Figure 3.5.22 Port C4, C5 92CA25-84 2007-02-28 TMP92CA25 (4) PC6 (KO8, EA24) Reset Direction control (on bit basis) PCCR write Internal data bus Funtcion control (on bit basis) PCFC write S Output latch S A Selector B PC6 (KO8, EA24) Open drain enable PC write EA24 S B Selector A PC read Figure 3.5.23 Port C6 (4) PC7 ( CSZF , EA25) Reset Direction control (on bit basis) PCCR write Funtcion control (on bit basis) Internal data bus PFFC write S Output latch S A Selector B C S B Selector A PC7 ( CSZF , EA25) PC write CSZF EA25 PC read Figure 3.5.24 Port C7 92CA25-85 2007-02-28 TMP92CA25 Port C Register 7 PC (0030H) Bit symbol Read/Write After reset PC7 6 PC6 5 PC5 4 PC4 R/W 3 PC3 2 PC2 1 PC1 0 PC0 Data from external port (Output latch register is set to "1") Port C Control Register 7 PCCR (0032H) Bit symbol Read/Write After reset Function 0 0 0 0 PC7C 6 PC6C 5 PC5C 4 PC4C W 3 PC3C 0 2 PC2C 0 1 PC1C 0 0 PC0C 0 Refer to following table Port C Function Register 7 PCFC (0033H) Bit symbol Read/Write After reset Function PC2 Setting 6 PC6F 5 PC5F 4 PC4F W 3 PC3F 0 2 PC2F 0 1 PC1F 0 0 PC0F 0 Refer to following table PC0 Setting PC7 Setting CSZF I/O PC6 Setting EA25 output at 0 1 Output port EA24 output at Port C Drive Register 7 PCDR (008CH) Bit symbol Read/Write After reset Function 1 1 1 1 PC7D 6 PC6D 5 PC5D 4 PC4D R/W 3 PC3D 1 2 PC2D 1 1 PC1D 1 0 PC0D 1 Input/Output buffer drive register for standby mode Note1: Read-modify-write is prohibited for the registers PCCR and PCFC. Note2: When setting PC3-PC0 pins to INT3-INT0 input, set PCDR Figure 3.5.25 Register for Port C 92CA25-86 2007-02-28 TMP92CA25 3.5.10 Port F (PF0 to PF7) Ports F0 to F6 are 7-bit general-purpose I/O ports. Resetting sets PF0 to PF6 to be input ports. It also sets all bits of the output latch register to "1". In addition to functioning as general-purpose I/O port pins, PF0 to PF6 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a "1" to the corresponding bit of the port F function register (PFFC). Port F7 is a 1-bit general-purpose output port. In addition to functioning as a general-purpose output port , PF7 can also function as the SDCLK output. Resetting sets PF7 to be an SDCLK output port. (1) Port F0 (TXD0), F1 (RXD0), F2 (SCLK0, CTS0 ) Ports F0 to F2 are general-purpose I/O ports. They also function as either SIO0. Each pin is detailed below. SIO mode (SIO0 module) PF0 PF1 PF2 TXD0 (Data output) RXD0 (Data input) SCLK0 (Clock input or output) UART, IrDA mode (SIO0 module) TXD0 (Data output) RXD0 (Data input) CTS0 (Clear to send) Reset Direction control (on bit basis) PFCR write Function control (on bit basis) Internal data bus PFFC write S Output latch S A BSelector PF0 (TXD0) Open drain set possible PFFC2 PF write TXD0 S B Selector A PF read Figure 3.5.26 Port F0 92CA25-87 2007-02-28 TMP92CA25 Reset Direction control (on bit basis) Internal data bus PFCR write S Output latch PF1 (RXD0) PF write S B Selector A PFFC PF read RXD0 P91RXD0 input Figure 3.5.27 Port F1 Reset Direction control (on bit basis) PFCR write Internal data bus S Output latch SCLK0 output PF write Function control (on bit basis) Selector S PF2 (SCLK0, CTS0 ) PFFC write S B Selector A PFFC PF read SCLK0 input, CTS0 input P92SCLK0 input Figure 3.5.28 Port F2 92CA25-88 2007-02-28 TMP92CA25 (2) PF3, PF4, PF5, PF6, PF7 Reset Direction control (on bit basis) PFCR write Function control (on bit basis) PFFC write S Output latch PF3 PF4 PF5 PF6 S B Selector A PF read Internal data bus PF write Figure 3.5.29 Port F3, F4. F5 and F6 Reset Internal data bus Function control (on bit basis) PFFC write S Output latch SDCLK PF write S A Selector B PF7 (SDCLK) PF read Figure 3.5.30 Port F7 92CA25-89 2007-02-28 TMP92CA25 Port F Register 7 PF (003CH) Bit symbol Read/Write After reset 1 PF7 6 PF6 5 PF5 4 PF4 R/W 3 PF3 2 PF2 1 PF1 0 PF0 Data from external port (Output latch register is set to "1") Port F Control Register 7 PFCR (003EH) Bit symbol Read/Write After reset Function 0 0 0 6 PF6C 5 PF5C 4 PF4C 3 PF3C W 0 Refer to following table 2 PF2C 0 1 PF1C 0 0 PF0C 0 Port F Functon Register 7 PFFC (003FH) Bit symbol Read/Write After reset Function 1 0 0 0 Refer to following table PF7F 6 PF6F 5 PF5F 4 PF4F W 3 PF3F 0 2 PF2F 0 1 PF1F 0 RXD0 pin selection 0: Port F1 1: Port 91 0 PF0F 0 Refer to following table PF2 Setting Input port, PF1 Setting 1 Output port Input port, RXD0 input from PF1, PF0 Setting 1 Output port 0 SCLK0, CTS0 input From PF2 pin at RXD0 input from P91 Reserved 1 PF5 Setting (Reserved) SCLK0 output 1 PF4 Setting 0 Input port (Reserved) 1 Output port (Reserved) PF3 Setting 92CA25-90 2007-02-28 TMP92CA25 Port F Functon Register 2 7 PFFC2 (003DH) Bit symbol Read/Write After reset Function - 6 5 4 3 2 - 1 0 PF0F2 W 0 Output buffer 0: CMOS 1: Open drain W 0 Always write "0" W 0 Always write "0" Port F Drive Register 7 PFDR (008FH) Bit symbol Read/Write After reset Function 1 1 1 1 PF7D 6 PF6D 5 PF5D 4 PF4D R/W 3 PF3D 1 2 PF2D 1 1 PF1D 1 0 PF0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PFCR, PFFC and PFFC2. Figure 3.5.31 Register for Port F 92CA25-91 2007-02-28 TMP92CA25 3.5.11 Port G (PG0 to PG3) PG0 to PG3 are 4-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter. PG2 and PG3 can also be used as the MX and MY pins for a touch screen interface. Internal data bus Port G read Conversion result register PG0 (AN0), PG1 (AN1), PG2 (AN2, MX), PG3 (AN3, MY, ADTRG ) AD converter Channel selector AD read ADTRG (only for PG3) (Only for PG2, PG3) TSICR0 Figure 3.5.32 Port G Port G Register 7 PG (0040H) Bit symbol Read/Write After reset 6 5 4 3 PG2 2 PG2 R 1 PG1 0 PG0 Data from external port Note: The input channel selection of the AD converter and the permission for ADTRG input are set by AD converter mode register ADMOD1. Port G Drive Register 7 PGDR (0090H) Bit symbol Read/Write After reset Function 1 6 5 4 3 PG3D R/W 2 PG2D 1 1 0 Input/Output buffer drive register for standby mode Figure 3.5.33 Register for Port G 92CA25-92 2007-02-28 TMP92CA25 3.5.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output ports. Resetting sets the output latch PJ to "1", and they output "1". PJ5 to PJ6 are 2-bit I/O ports. In addition to functioning as a port, port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM and SDCKE), SRAM ( SRWR , SRLLB , SRLUB ) and NAND flash (NDALE and NDCLE). The above settings are made using the function register PJFC. However, H either SDRAM or SRAM output signals for PJ0 to PJ2 are selected automatically according to the setting of the memory controller. Reset Function control 2 (on bit basis) PJFC2 write Internal data bus Function control (on bit basis) S PJFC write Selector Output latch PJ0 ( SDRAS , SRLLB ) PJ1 ( SDCAS , SRLUB ) PJ2 ( SDWE , SRWR ) PJ3 (SDLLDQM) PJ4 (SDLUDQM) PJ7 (SDCKE) PJ write SRLLB , SRLUB , SRWR SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE PJ read Figure 3.5.34 Port J0, J1, J2, J3, J4 and J7 92CA25-93 2007-02-28 TMP92CA25 Reset Direction control (on bit basis) PJCRwrite Function control (on bit basis) PJFC write S Output latch Selector PJ write NDALE, NDCLE S B Selector A Internal data bus S PJ5 (NDALE), PJ6 (NDCLE) PJ read Figure 3.5.35 Port J5 and J6 92CA25-94 2007-02-28 TMP92CA25 Port J Register 7 PJ (004CH) Bit symbol Read/Write After reset 1 Data from external port (Output latch register is set to "1") 1 PJ7 6 PJ6 5 PJ5 4 PJ4 R/W 3 PJ3 2 PJ2 1 PJ1 0 PJ0 1 1 1 1 Port J Control Register 7 PJCR (004EH) Bit symbol Read/Write After reset Function 0 6 PJ6C W 5 PJ5C 0 4 3 2 1 0 0: Input 1: Output Port J Function Register 7 PJFC (004FH) Bit symbol Read/Write After reset Function 0 0: Port 1: SDCKE at 6 PJ6F 0 0: Port 1: NDCLE at 5 PJ5F 0 0: Port 4 PJ4F W 0 0: Port 3 PJ3F 0 0: Port 2 PJ2F 0 0: Port 1 PJ1F 0 0: Port 1: SDCAS , SRLUB 0 PJ0F 0 0: Port 1: SRRAS , SRLLB PJ7F 1: NDALE at 1: SDLUDQM 1: SDLLDQM 1: SDWE , Port J Drive Register 7 PJDR (0093H) Bit symbol Read/Write After reset Function 1 1 1 1 PJ7D 6 PJ6D 5 PJ5D 4 PJ4D R/W 3 PJ3D 1 2 PJ2D 1 1 PJ1D 1 0 PJ0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PJCR and PJFC. Figure 3.5.36 Register for Port J 92CA25-95 2007-02-28 TMP92CA25 3.5.13 Port K (PK0 to PK7) Port K is a 4-bit output port. Resetting sets the output latch PK to "0", and PK0 to PK3 pins output "0". PK4 to PK7 are 4-bit input ports. Resetting sets the PLCR to "0", and set input port. In addition to functioning as an output port, port K also functions as output pins for an LCD controller (LCP0, LLP, LFR and LBCD) and pin for an SPI controller (SPCLK, SPCS , SPDO and SPDI). The above settings are made using the function register PKFC. Reset Function control Internal data bus (on bit basis) PKFC write S Output latch A Selector PK write B LCP0, LLP, LFR, LBCD Output buffer PK0 (LCP0) PK1(LLP) PK2 (LFR) PK3 (LBCD) PK read Figure 3.5.37 Port K0 to K3 92CA25-96 2007-02-28 TMP92CA25 Reset Direction contorl (on bit basis) PKCR write Function control (on bit basis) PKFC write S Output latch PK4 (SPDI) Internal data bus PK write S B Selector A PK read SPDI input Figure 3.5.38 Port K4 Reset Direction control (on bit basis) PKCR write Function control (on bit basis) PKFC write S Output latch S A Selector B Internal data bus PK5 (SPDO) PK6 ( SPCS ) PK7 (SPCLK) PK write SPDO SPCS SPCLK S B Selector A PJ read Figure 3.5.39 Port K5 to K7 92CA25-97 2007-02-28 TMP92CA25 Port K Register 7 PK (0050H) Bit symbol Read/Write After reset Data from external port (Output latch register is cleared to "0") PK7 6 PK6 5 PK5 4 PK4 R/W 3 PK3 2 PK2 1 PK1 0 PK0 0 0 0 0 Port K Control Register 7 PKCR (0052H) Bit symbol Read/Write After reset Function 0 0 PK7C 6 PK6C W 5 PK5C 0 4 PK4C 0 3 2 1 0 0: Input 1: Output Port K Function Register 7 PKFC (0053H) Bit symbol Read/Write After reset Function 0 0: Port 1: SPCLK output 0 0: Port 1: SPCS output 0 0: Port 1: SPDO output 0 0: Port 1: SPDI output PK7F 6 PK6F 5 PK5F 4 PK4F W 3 PK3F 0 0: Port 1: LBCD 2 PK2F 0 0: Port 1: LFR 1 PK1F 0 0: Port 1: LLP 0 PK0F 0 0: Port 1: LCP0 PK5 Setting PK4 Setting 0 1 PK7 Setting Input port Reserved Output port SPDO output 0 1 PK6 Setting Input port SPDI input Output port Reserved 0 1 0 1 0 1 Input port Reserved Output port SPCLK output 0 1 Input port Reserved Output port SPCS output Port K Drive Register 7 PKDR (0094H) Bit symbol Read/Write After reset Function 1 1 1 1 PK7D 6 PK6D 5 PK5D 4 PK4D R/W 3 PK3D 1 2 PK2D 1 1 PK1D 1 0 PK0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the register PKFC. Figure 3.5.40 Register for Port K 92CA25-98 2007-02-28 TMP92CA25 3.5.14 Port L (PL0 to PL7) PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to "0", and PL0 to PL3 pins output "0". PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR. Resetting resets the control register PLCR to "0" and sets PL4 to PL7 to input ports. In addition to functioning as a general-purpose I/O port, port L can also function as a data bus for an LCD controller (LD0 to LD7) and external bus open request input ( BUSRQ ),answer output ( BUSAK ). The above settings are made using the function register PLFC. Reset Function control (on bit basis) Internal data bus PLFC write R Output latch S A PL write LD0 to LD3 Selector B PL0 to PL3 (LD0 to LD3) PL read Figure 3.5.41 Register for Port L0 to L3 Reset Direction control (on bit basis) PLCR write Internal data bus Function control (on bit basis) PLFC write S Output latch S A Selector B S B Selector PL4 to PL5 (LD4 to LD5) PL write LD4 to LD5 PL read A Figure 3.5.42 Register for Port L4 to L5 92CA25-99 2007-02-28 TMP92CA25 Reset Direction control (on bit basis) PLCR write Internal data bus Functino control (on bit basis) PLFC write R Output latch S A Selector B S B Selector PL6 (LD6, BUSRQ ) PL write BUSRQ PL read A BUSRQ Figure 3.5.43 Port L6 Reset Direction control (on bit basis) PLCR write Function control (on bit basis) Internal data bus PLFC write R Output latch S A Selector B PL7 (LD7, BUSAK ) PL write S A Selector B S B Selector A LD7 BUSAK PL read Figure 3.5.44 Port L7 92CA25-100 2007-02-28 TMP92CA25 Port L Register 7 PL (0054H) Bit symbol Read/Write After reset Data from external port (Output latch register is cleared to "0") PL7 6 PL6 5 PL5 4 PL4 R/W 3 PL3 2 PL2 1 PL1 0 PL0 0 0 0 0 Port L Control Register 7 PLCR (0056H) Bit symbol Read/Write After reset Function 0 0 PL7C 6 PL6C W 5 PL5C 0 4 PL4C 0 3 2 1 0 0: Input 1: Output Port L Function Register 7 PLFC (0057H) Bit symbol Read/Write After reset Function 0 0 0 0 Refer following table PL5 Setting 6 PL6F 5 PL5F 4 PL4F W 3 PL3F 0 2 PL2F 0 PL4 Setting 1 PL1F 0 0 PL0F 0 PL7F 0: Port 1: Data bus for LCDC (LD3 to LD0) 1 0 1 PL7 Setting Input port Reserved Output port LD5 output 0 1 PL6 Setting Input port Reserved Output port LD4 output 0 1 0 1 0 1 Input port Output port LD7 output 0 1 Input port Output port LD6 output BUSAK output BUSRQ input Port L Drive Register 7 PLDR (0095H) Bit symbol Read/Write After reset Function 1 1 1 1 PL7D 6 PL6D 5 PL5D 4 PL4D R/W 3 PL3D 1 2 PL2D 1 1 PL1D 1 0 PL0D 1 Input/Output buffer drive register for standby mode Note1: Read-modify-write is prohibited for the registers PLCR and PLFC. Note2: When Port L are used at LD0 to LD7, If set PL6 pin to BUSRQ function input temporarily, CPU may not be operate normally. Therefore, set registers by following order. Order (1) (2) Register PLCR PLFC Setting value 1 1 Figure 3.5.45 Port L Register 92CA25-101 2007-02-28 TMP92CA25 3.5.15 Port M (PM1 to PM2) PM1 and PM2 are 2-bit output ports. Resetting sets the output latch PM to "1", and PM1 and PM2 pins output "1". In addition to functioning as a port, port M also functions as output pins for the RTC alarm ( ALARM ), and as the output pin for the melody/alarm generator (MLDALM, MLDALM ). The above settings are made using the function register PMFC. Only PM2 has two output functions - ALARM and MLDALM . These are selected using PM Reset Function control (on bit basis) Internal data bus PMFC write S Output latch S A Selector B PM write PM1 (MLDALM) PM read MLDALM Figure 3.5.46 Port M1 Reset Function control (on bit basis) PMFC write Internal data bus S Output latch A S Selector PM2 ( ALARM , MLDALM ) PM write B PM read S MLDALM A Selector ALARM B Figure 3.5.47 Port M2 92CA25-102 2007-02-28 TMP92CA25 Port M Register 7 PM (0058H) Bit symbol Read/Write After reset 1 6 5 4 3 2 PM2 R/W 1 PM1 1 0 Port M Function Register 7 PMFC (005BH) Bit symbol Read/Write After reset Function 0 0: Port 1: ALARM at 6 5 4 3 2 PM2F W 1 PM1F 0 0: Port 1: MLDALM output 0 Port M Drive Register 7 PMDR (0096H) Bit symbol Read/Write After reset Function 1 6 5 4 3 2 PM2D R/W 1 PM1D 1 0 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the register PMFC. Figure 3.5.48 Register for Port M 92CA25-103 2007-02-28 TMP92CA25 3.5.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port N to an input port. In addition to functioning as a general-purpose I/O port, Port N can also as interface pin for key-board (KO0 to KO7). This function can set to open-drain type output buffer. Reset Direction control (on bit basis) PNCR write Internal data bus Function control (on bit basis) PNFC write S Output latch Open drian enable PN write S B Selector PN read A PN0 to PN7 (KO0 to KO7) Figure 3.5.49 Port N 92CA25-104 2007-02-28 TMP92CA25 Port N register 7 PN (005CH) Bit symbol Read/Write After reset PN7 6 PN6 5 PN5 4 PN4 R/W 3 PN3 2 PN2 1 PN1 0 PN0 Data from external port (Output latch register is set to "1") Port N Control Register 7 PNCR (005EH) Bit symbol Read/Write After reset Function 0 0 0 0 PN7C 6 PN6C 5 PN5C 4 PN4C W 3 PN3C 0 2 PN2C 0 1 PN1C 0 0 PN0C 0 0: Input 1: Output Port N Function Register 7 PNFC (005FH) Bit symbol Read/Write After reset Function 0 0 0 0 PN7F 6 PN6F 5 PN5F 4 PN4F W 3 PN3F 0 2 PN2F 0 1 PN1F 0 0 PN0F 0 0: CMOS output 1:Open drain output Port N Drive Register 7 PNDR (0097H) Bit symbol Read/Write After reset Function 1 1 1 1 PN7D 6 PN6D 5 PN5D 4 PN4D R/W 3 PN3D 1 2 PN2D 1 1 PN1D 1 0 PN0D 1 Input/Output buffer drive register for standby mode Note: Read modify write is prohibited for the registers PNCR and PNFC. Figure 3.5.50 Register for Port N 92CA25-105 2007-02-28 TMP92CA25 3.6 Memory Controller Functions The TMP92CA25 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for the 4-block address area (block 0 to 3). * * * * SRAM or ROM: All CS blocks (CS0 to CS3) are supported. SDRAM Page ROM NAND flash : Only either CS1 or CS2 blocks are supported. : Only CS2 blocks are supported. : CS setting is not needed. 3.6.1 (2) Connecting memory specifications Specifies SRAM, ROM and SDRAM as memories that connect with the selected address areas. (3) Data bus width selection Whether 8 bits, 16 bits is selected as the data bus width of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in the 6 modes listed below. 0 waits, 1 wait, 2 waits, 3 waits, 4 waits N waits (controls with WAIT pin) 3.6.2 Control Register and Operation after Reset Release This section describes the registers that control the memory controller, the state following reset release and the necessary settings. (1) Control register The control registers of the memory controller are as follows and in Table 3.6.1 and Table 3.6.2. * Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller; the memory type that is connected, the number of waits which are read and written. Memory start address register: MSARn (n = 0 to 3) Sets a start address in the selected address areas. Memory address mask register: MAMR (n = 0 to 3) Sets a block size in the selected address areas. Page ROM control register: PMEMCR Sets the method of accessing page ROM. Memory controls control register: MEMCR0 Sets waveform selection of RD pin and setting method of CS0 * * * * to CS3 . 92CA25-106 2007-02-28 TMP92CA25 Table 3.6.1 Control Register 7 B0CSL (0140H) Bit symbol Read/Write After reset B0CSH (0141H) Bit symbol Read/Write After reset MAMR0 (0142H) Bit symbol Read/Write After reset MSAR0 (0143H) Bit symbol Read/Write After reset B1CSL (0144H) Bit symbol Read/Write After reset B1CSH (0145H) Bit symbol Read/Write After reset MAMR1 (0146H) Bit symbol Read/Write After reset MSAR1 (0147H) Bit symbol Read/Write After reset B2CSL (0148H) Bit symbol Read/Write After reset B2CSH (0149H) Bit symbol Read/Write After reset MAMR2 (014AH) Bit symbol Read/Write After reset MSAR2 (014BH) Bit symbol Read/Write After reset B3CSL (014CH) Bit symbol Read/Write After reset B3CSH (014DH) Bit symbol Read/Write After reset MAMR3 (014EH) Bit symbol Read/Write After reset MSAR3 (014FH) Bit symbol Read/Write After reset 1 1 1 1 1 M3S23 1 M3S22 1 M3S21 1 M3S20 R/W 1 1 1 1 0 M3V22 0 (Note) M3V21 0 (Note) M3V20 0 M3V19 R/W 1 M3S19 1 M3S18 1 M3S17 1 M3S16 B3E 0 - 1 1 B3WW2 1 B3WW1 W 1 - 0 B3REC W 0 M3V18 0 M3V17 0 M3V16 0 M3V15 B3OM1 0 B3OM0 1 B3WW0 1 M2S23 1 M2S22 1 M2S21 1 M2S20 R/W 1 1 B3WR2 1 B3WR1 W 1 B3BUS1 0 B3BUS0 1 B3WR0 1 M2V22 0 M2V21 0 (Note) M2V20 0 M2V19 R/W 1 M2S19 1 M2S18 1 M2S17 1 M2S16 B2E 0 B2M 1 1 B2WW2 1 B2WW1 W 1 - 0 B2REC W 0 M2V18 0 M2V17 0 M2V16 0 M2V15 B2OM1 0 B2OM0 1 B2WW0 1 M1S23 1 M1S22 1 M1S21 1 M1S20 R/W 1 1 B2WR2 1 B2WR1 W 1 B2BUS1 0 B2BUS0 1 B2WR0 0 M1V21 0 (Note) M1V20 0 (Note) M1V19 0 M1V18 R/W 1 M1S19 1 M1S18 1 M1S17 1 M1S16 B1E 0 - 1 1 B1WW2 1 B1WW1 W 1 - 0 B1REC W 0 M1V17 0 M1V16 0 M1V15 to M1V9 0 M1V8 B1OM1 0 B1OM0 1 B1WW0 1 M0S23 1 M0S22 1 M0S21 1 M0S20 R/W 1 1 B1WR2 1 B1WR1 W 1 B1BUS1 0 B1BUS0 1 B1WR0 0 M0V20 0 (Note) M0V19 0 (Note) M0V18 0 M0V17 R/W 1 M0S19 1 M0S18 1 M0S17 1 M0S16 B0E 0 - 6 B0WW2 5 B0WW1 W 1 - 4 B0WW0 0 B0REC W 3 2 B0WR2 0 1 B0WR1 W 1 B0BUS1 0 M0V14 to M0V9 0 B0WR0 0 B0BUS0 0 M0V8 B0OM1 0 M0V16 B0OM0 0 M0V15 Note 1: Always write "0". Note 2:Read-modify-write is prohibited for BnCS0 and BnCSH (n = 0 to 3) registers. 92CA25-107 2007-02-28 TMP92CA25 Table 3.6.2 Control Register 7 BEXCSH (0159H) Bit symbol Read/Write After reset BEXCSL (0158H) Bit symbol Read/Write After reset PMEMCR Bit symbol (0166H) Read/Write After reset MEMCR0 (0168H) Bit symbol Read/Write After reset Note: Read-modify-write is prohibited for BEXCSH and BEXCSL registers. 0 0 BEXWW2 BEXWW1 W 1 0 OPGE 0 OPWR1 0 0 OPWR0 R/W 0 CSDIS 1 RDTMG1 R/W 0 0 0 RDTMG0 BEXWW0 0 0 BEXWR2 6 5 4 3 BEXOM1 2 BEXOM0 W 1 BEXBUS1 0 BEXWR1 W 1 PR1 0 BEXBUS0 0 BEXWR0 0 PR0 (2) Operation after reset release The start data bus width is determined by the state of AM1/AM0 pins just after reset release. The external memory is then accessed as follows AM1 0 0 1 1 AM0 0 1 0 1 Start Mode Don't use this setting Start with 16-bit data bus (Note) Start with 8-bit data bus (Note) Don't use this setting Note: The memory to be used on starting after reset must be either NOR flash or masked ROM. NAND flash and SDRAM cannot be used. AM1/AM0 pins are valid only just after reset release. In other cases, the data bus width is set by the control register 92CA25-108 2007-02-28 TMP92CA25 3.6.3 Basic Functions and Register Setting This section describes the setting of the block address area, the connecting memory and the number of waits out of the memory controller's functions. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares the register value and the address every bus cycle. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The value that is set to the register is compared with the block address area on the bus. If the result is a match, the memory controller sets the chip select signal (CSn) to "low". (i) Memory start address register setting The MS23 to MS16 bits of the memory start address register correspond with addresses A23 to A16 respectively. The lower start addresses A15 to A0 are always set to address 0000H. Therefore the start addresses of the block address area are set to all 64 Kbytes of addresses 000000H to FF0000H. (ii) Memory address mask register setting The memory address mask register determines whether an address bit is compared or not. In register setting, "0" is "compare", and "1" is "do not compare". The address bits that can be set depends on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 3: A22 to A15 The upper bits are always compared. The block address area size is determined by the result of the comparison. The size to be set depending on the block address area is as follows. Size (bytes) CS area CS0 CS1 CS2 to CS3 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M Note: After reset release, only the control register of the block address area 2 is valid. The control register of block address area 2 has the 92CA25-109 2007-02-28 TMP92CA25 (iii) Example of register setting To set the block address area 64 Kbytes from address 110000H, set the register as follows. MSAR1 Register Bit Bit symbol Specified value 7 M1S23 0 6 M1S22 0 5 M1S21 0 4 M1S20 1 3 M1S19 0 2 M1S18 0 1 M1S17 0 0 M1S16 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are set to "0". Therefore, if MSAR1 is set to the above mentioned value, the start address of the block address area is set to address 110000H. MAMR1 Register Bit Bit symbol Specified value 7 M1V21 0 6 M1V20 0 5 M1V19 0 4 M1V18 0 3 M1V17 0 2 M1V16 0 1 M1V15 to M1V9 0 M1V8 1 0 M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 are set whether addresses A21 to A16 and A8 are compared or not. In register setting, "0" is "compare", and "1" is "do not compare". M1V15 to M1V9 bits determine whether addresses A15 to A9 are compared or not with bit 1. A23 and A22 are always compared. When set as above, A23 to A9 are compared with the value that is set as the start addresses. Therefore, 512 bytes (addresses 110000H to 1101FFH) are set as block address area 1, and if it is compared with the addresses on the bus, the chip select signal CS1 is set to "low". The other block address area sizes are specified in the same way. A23 and A22 are always compared with block address area 0. Whether A20 to A8 are compared or not is determined by the register. Similarly, A23 is always compared with block address areas 2 to 5. Whether A22 to A15 are compared or not is determined by the register. Note 1: When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 Note 2: If an address area other than CS0 to CS3 is accessed, this area is regarded as CSEX . Therefore, wait number and data bus width controls follow the setting of CSEX (BEXCSH, BEXCSL register). 92CA25-110 2007-02-28 TMP92CA25 (2) Connection memory specification Setting the 0 0 1 1 0 1 0 1 Reserved Reserved SDRAM Function SRAM/ROM (Default) Note 1: SDRAM should be set to block either 1 or 2. Note 2: Set "00" for NAND flash, RAM built-in LCDD. (3) Data bus width specification The data bus width is set for every block address area. The bus size is set by setting the control register (BnCSH) 0 0 1 1 BnBUS 0 0 1 0 1 Function 8-bit bus mode (Default) 16-bit bus mode Reserved Don't use this setting Note: SDRAM should be set to either "01" (16-bit bus). This method of changing the data bus width depending on the accessing address is called "dynamic bus sizing". The part of the data bus to which the data is output depends on the data size, baus width and start address. Number of external data bus pin in TMP92CA25 are 16 pins. Therefore, please ignore case of memory data size is 32 in each tables. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive addresses, do not execute an access to both memories with one command. 92CA25-111 2007-02-28 TMP92CA25 Operand Data Size (bit) Operand Start Address 4n + 0 4n + 1 Memory Data Size (bit) 8/16/32 8 16/32 8/16 32 8 16 32 8 16/32 8 16 32 8 16 32 8 16 32 CPU Address 4n + 0 4n + 1 4n + 1 4n + 2 4n + 2 4n + 3 4n + 3 4n + 3 (1) 4n + 0 (2) 4n + 1 4n + 0 (1) 4n + 1 (2) 4n + 2 (1) 4n + 1 (2) 4n + 2 4n + 1 (1) 4n + 2 (2) 4n + 1 4n + 2 4n + 2 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 0 (2) 4n + 2 4n + 0 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 1 (2) 4n + 2 (3) 4n + 4 (1) 4n + 1 (2) 4n + 4 (1) 4n + 2 (2) 4n + 3 (3) 4n + 4 (4) 4n + 5 (1) 4n + 2 (2) 4n + 4 (1) 4n + 2 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (3) 4n + 5 (4) 4n + 6 (1) 4n + 3 (2) 4n + 4 (3) 4n + 6 (1) 4n + 3 (2) 4n + 4 xxxxx CPU Data D31 to D24 D23 to D16 D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 b15 to b8 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx xxxxx b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b31 to b24 b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b23 to b16 b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b31 to b24 D7 to D0 b7 to b0 b7 to b0 xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b7 to b0 b15 to b8 b7 to b0 xxxxx b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 xxxxx b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b15 to b8 8 4n + 2 4n + 3 4n + 0 4n + 1 16 4n + 2 4n + 3 4n + 0 8 16 32 8 4n + 1 16 32 32 4n + 2 8 16 32 4n + 3 8 16 32 xxxxx: During a read, data input to the bus ignored. At write, the bus is at high impedance and the write strobe signal remains non active. 92CA25-112 2007-02-28 TMP92CA25 (4) Wait control The external bus cycle completes a wait of at least two states (100 ns at fSYS = 20 MHz). Setting the |